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ASIP eUpdate, June 2016

Overview

Welcome to the latest issue of the ASIP eUpdate Newsletter, our bi-annual publication to keep you informed on topics related to application-specific instruction-set processor (ASIP) design. ASIPs are a proven solution for domain-specific/application-optimized processors, and often serve as a more flexible yet equally efficient alternative to fixed RTL implementations, often referred to as programmable accelerators.

ASIPs come with an architecture and instruction set tuned for a specific application domain. They rely on techniques similar to those used in the design of hardware accelerators to reach high performance and low power: heavy use of parallelism and specialized datapath elements. Yet ASIPs retain software programmability within their application domain, resulting in C/C++ programmable processors and accelerators with the lowest power possible.

What’s New in ASIP Designer?

The March release of ASIP Designer (2016.03) is available, and the September release (2016.09) is already on the horizon. The following highlights some new features.

LLVM compiler frontend

The LLVM compiler infrastructure offers broad language support, including C and C++, and a large number of processor independent optimizations. To exploit these benefits, we developed a new compiler front-end based on the LLVM infrastructure, to be combined with the retargetable compiler backend of ASIP Designer. We extended the LLVM release in several ways, to support the full architectural freedom offered by ASIP Designer. These extensions include:

Instantaneous adaption to the ASIP Designer processor model (Compiler-in-the-Loop)
Increased flexibility in data types, supporting non-power-of-two C built-in types. For example, char, short, long, and long long can have a width that is not a power of two
Exploitation of all application types provided in the ASIP Designer processor model, including vector (SIMD) data types and user-defined (custom) data types
Multiple address spaces. The multiple memories defined in nML are accessible in the LLVM flow, using the same memory specifiers. The different address spaces can be associated with different pointer widths and different addressable unit sizes. So, data memories are no longer restricted to be byte addressable
Native Pointer Support. The ASIP Designer processor model may implement pointer arithmetic differently than integer arithmetic. For example, pointers can have a different width and can be mapped to dedicated address generation units and corresponding registers
Our LLVM flow automatically fully exploits the underlying processor model, involving optimizations like selection of zero-overhead loop instructions and aggressive software pipelining

ASIP Designer comes with extensive C and C++ library support providing both a full-featured stack as well as a lightweight stack. The lightweight stack is tailored to the needs of embedded designs and results in significant savings on both cycle-count and instruction words.

Instruction set simulator (ISS) performance increase

ASIP Designer applies a single-source model approach using nML. All aspects of an ASIP are derived from one single nML model, so there is no need to keep multiple models in sync. This is also true for the two variants of an instruction-set simulator (ISS), which might be either cycle-accurate (CA) or instruction-accurate (IA). Both simulators are generated from the same nML model.

The 2016.03 release includes the initial version of a cycle-accurate simulator using just-in-time (JIT) compilation. Compared to the 2015.06 release, we see simulation performance increases of 2X to 18X, depending on the processor architecture. And of course, no changes to the nML model are required, so these improvements apply immediately to your existing designs.
The 2016.09 release will include the initial version of the instruction-accurate simulator using JIT. With no modification of the model necessary, and with no need for pre-compiling the application executable with the simulation model, you can move to an instruction-accurate simulator. Should you be interested in an evaluation, contact us for a beta version right away.
For completeness: For tuning your application, ASIP Designer also supports native simulation. Native simulation means a bit-accurate execution of your application running on your host machine, featuring the fastest fully functional, bit-level correct simulation possible, using all ASIP-specific data types and operators.

New Example Model: RISC-V

The example model library has been extended with a new model featuring the RISC-V instruction-set architecture. As with all other example models, the RISC-V model is provided in nML source code and can serve as the starting point for application-specific extensions and modifications. With ASIP Designer users can generate both synthesizable RTL, including JTAG debug logic, and a fully featured software development kit (SDK) including a C/C++ compiler, cycle-accurate and instruction-accurate instruction-set simulators, assembler / disassembler, and debugger.

There are many more enhancements that came with the 2016.03 release. For more features and additional details about the topics listed above, please refer to the ASIP Designer release notes, send a note to asipsupport@synopsys.com, or contact your local Synopsys representative. We will be happy to arrange for a specific update presentation. Also be sure to check out the updated and extended ASIP Designer data sheet, to get an overview of the features and capabilities of ASIP Designer.

Example Processor Models: SIMD processing using Tvec

With the previous newsletter (December 2015) we gave an overview of the example models available with ASIP Designer. Designers can choose from this extensive library of example ASIP models, which are provided as nML source code. These models are an excellent reference to learn how to model certain processor functionalities in nML, to explain how the compiler can take advantage of the architectural specialization, and how to leverage the generated SDK. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration, and customer-specific production designs. Starting with the current newsletter, we will drill one level deeper, giving an overview of specific example models. In this newsletter, we start with Tvec.

Tvec is an entire family of example models, all featuring the concept of single-instruction, multiple-data (SIMD). SIMD is an extremely efficient way to add parallelism with very little control. Its concept is widely applicable to many different application domains, including wireless, video and image processing – basically everywhere where an algorithm is most naturally described as a vector (therefore the name, Tvec). While the SIMD concept is fairly generic, different application domains require different implementations of SIMD – indeed leading to application-specific processors.

The list of features supported by Tvec is too long to list here, however the following is a subset of the basic and “special” features that are supported:

Support for wide SIMD: In the example implementation a 128 bit vector type can be partitioned into lanes of 16 or 32 bit, with efficient resource sharing in the arithmetic units.
Vector predication: A normal vector instruction executes N identical scalar operations in parallel. In case of a predicated vector instruction, one or more of these scalar operations can be disabled, based on the bits of a condition vector. Vector predication is used to implement local conditional computations in the code. It is often beneficial for image and video processing.
Vector predicate stack: Vector predication is typically limited to a single condition or a combination of a few conditions. SIMD execution of complex image processing applications requires that nested conditions are supported. This is supported by adding a stack to store condition vectors. The same stack can also be used to support loop control.
Vector addressing: This is the ability to load or store a vector where the address is also a vector. In the case of gather/scatter each element of a vector address can point to any scalar word in the data memory.
OpenCL: The vector predicate stack and gather/scatter memory access are key architecture features that enable the efficient compilation of OpenCL vector code. On Tvec, we demonstrate how ASIP Designer's OpenCL front end can be used to implement whole function vectorization for OpenCL kernel functions.
Auto vectorization: Next to the OpenCL capability, ASIP Designer also support auto vectorization as part of its LLVM based compiler front end.

All Tvec examples come with a fully featured SDK, including a C/C++compiler that utilizes the specialized vector capabilities, a cycle-accurate and instruction-accurate simulator, and a graphical debugging environment.

For more details on these example models, or information on Tvec or any other example model, send a note to asipsupport@synopsys.com, or contact your local Synopsys representative.

Webinars

Register now for our upcoming webinar: Programmable Accelerators for Modern SoCs: When Hardware Accelerators Also Require Flexibility, taking place on July 13th at 8:00 am PT. Offloading performance/power-critical functions from high-performance processor cores into specialized accelerators is common in today’s SoC designs. These accelerators are specifically designed to meet the performance and power requirements of the target application. While accelerators are commonly implemented as fixed-function RTL designs, there is a growing need for more flexible, programmable accelerators. In this webinar we will cover why ASIPs can address this need, and how RTL designers can quickly adopt the ASIP approach.

The following webinars are available, to be viewed on-demand:

Webinar: Automatically Generate a Software Development Kit for Your In-House Processor

Webinar: How to Optimize Your Application-Specific Processor (ASIP)

White papers

Register to read our latest white paper: Software Development Kits (SDKs) for Proprietary Processors – Why They Matter, What It Takes to Develop Them

Teams designing in-house processors often find that they have limited time and expertise to create, deploy, maintain and support an SDK for their processor. Starting from a requirement specification for modern SDKs, this white paper describes how a tool-based approach using ASIP Designer can significantly enhance productivity. This is even true for existing processors that lack a sufficient SDK. By modeling the legacy processor in nML and using ASIP Designer, the time and effort needed to create the SDK can be significantly reduced, and Synopsys’ deployment and support infrastructure can be leveraged.

Also register to download the following whitepapers: