With the previous newsletter (December 2015) we gave an overview of the example models available with ASIP Designer. Designers can choose from this extensive library of example ASIP models, which are provided as nML source code. These models are an excellent reference to learn how to model certain processor functionalities in nML, to explain how the compiler can take advantage of the architectural specialization, and how to leverage the generated SDK. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration, and customer-specific production designs. Starting with the current newsletter, we will drill one level deeper, giving an overview of specific example models. In this newsletter, we start with Tvec.
Tvec is an entire family of example models, all featuring the concept of single-instruction, multiple-data (SIMD). SIMD is an extremely efficient way to add parallelism with very little control. Its concept is widely applicable to many different application domains, including wireless, video and image processing – basically everywhere where an algorithm is most naturally described as a vector (therefore the name, Tvec). While the SIMD concept is fairly generic, different application domains require different implementations of SIMD – indeed leading to application-specific processors.
The list of features supported by Tvec is too long to list here, however the following is a subset of the basic and “special” features that are supported:
- Support for wide SIMD: In the example implementation a 128 bit vector type can be partitioned into lanes of 16 or 32 bit, with efficient resource sharing in the arithmetic units.
- Vector predication: A normal vector instruction executes N identical scalar operations in parallel. In case of a predicated vector instruction, one or more of these scalar operations can be disabled, based on the bits of a condition vector. Vector predication is used to implement local conditional computations in the code. It is often beneficial for image and video processing.
- Vector predicate stack: Vector predication is typically limited to a single condition or a combination of a few conditions. SIMD execution of complex image processing applications requires that nested conditions are supported. This is supported by adding a stack to store condition vectors. The same stack can also be used to support loop control.
- Vector addressing: This is the ability to load or store a vector where the address is also a vector. In the case of gather/scatter each element of a vector address can point to any scalar word in the data memory.
- OpenCL: The vector predicate stack and gather/scatter memory access are key architecture features that enable the efficient compilation of OpenCL vector code. On Tvec, we demonstrate how ASIP Designer's OpenCL front end can be used to implement whole function vectorization for OpenCL kernel functions.
- Auto vectorization: Next to the OpenCL capability, ASIP Designer also support auto vectorization as part of its LLVM based compiler front end.
All Tvec examples come with a fully featured SDK, including a C/C++compiler that utilizes the specialized vector capabilities, a cycle-accurate and instruction-accurate simulator, and a graphical debugging environment.
For more details on these example models, or information on Tvec or any other example model, send a note to asipsupport@synopsys.com, or contact your local Synopsys representative.
