RISC-V Summit 2025

The rapid growth of RISC-V in automotive and IoT exposes a key challenge: firmware fragmentation. For microcontrollers, running applications with hardware-enforced privilege separation is essential for safety and security. This requires a trusted M-mode runtime, but without a standard, developers create proprietary solutions, hindering code reuse and complicating RTOS portability. 
 
The Supervisor Binary Interface (SBI) proves the power of a standard interface for application-class processors. While the SBI is tailored for such systems, its success provides a blueprint. The embedded domain urgently needs an equivalent built for the unique resource and real-time constraints of microcontrollers. 
 
This session will launch a community effort to solve this. We will define the key requirements for a standard "Embedded-SBI" or "μSBI" (for microcontrollers), learning from the SBI’s principles. We will outline an interface that prioritizes modularity, deterministic performance, and robust hardware isolation. Join this crucial conversation to help shape a foundational standard for the embedded RISC-V ecosystem.

Simulation throughput has long been the bottleneck in achieving verification closure. Complex RISC-V designs have exacerbated this problem, requiring long-running tests and complex stimulus to ensure that the design is bug free. This talk presents a case study using an industry-standard test generator adapted for use with hardware emulation. The case study uses the open-source XiangShan RISC-V core as the example design under test. The presentation will outline the techniques employed to achieve comprehensive testing and high verification throughput while presenting evidence of the effectiveness of this approach at finding bugs. After attending the talk attendees facing similar challenges should feel empowered to try this approach.

This presentation discusses the development of virtual development kits to accelerate software development, test, and integration for high performance compute. It will describe the steps taken to build the models for the virtual prototype of the chiplet and ultimately achieve Linux boot to enable further testing of compute peripherals. The work provides a proven reference flow for software development that will benefit the RISC-V ecosystem.

Location: Synopsys Exhibit Booth, P5

Interested in learning more about Synopsys RISC-V solutions? Stop by the booth to chat with our engineering leaders on how Synopsys can help you accelerate your next design.

Moderated by Andrew Moore, Director of Marketing, RISC-V International

RISC-V provides the ability to provide organizations of all sizes with greater flexibility and more opportunity for custom compute. We are seeing rapid adoption in a wide range of markets from automotive to mobile to data center, to aeronautics and space! Companies around the world are innovating for and on RISC-V to drive the era of open compute. In this session, we will hear directly from companies who have recently launched new solutions helping to power the era of open compute and how RISC-V helps them differentiate.

Advanced Instruction Fusion introduces a novel mechanism for fusing common pairs of RISC-V instructions, aimed at improving processor pipeline efficiency, particularly for resource constrained embedded processors. It extends a single-issue in-order processor to support dual instruction issue by fusing instructions from different functional units. Importantly, this does not introduce new instructions but maintains full RISC-V compatibility and is software agnostic, ensuring seamless integration with existing software and hardware environments. By reducing pipeline overhead and simplifying instruction handling, Advanced Instruction Fusion delivers significant efficiency improvements for embedded processors. The approach also provides adaptable design principles and can be extended from dual to multi-instruction fusion options to benefit RISC-V processor implementations across the ecosystem.

Synopsys has solutions for RISC-V developers to help from the initial architecting of the project (architecture exploration and RISC-V processor IP) through verification to software development. The processor IP is based on 25+ years of customer success, and the tools and models have been used by over 150 organizations, with verification solutions used for the tape out of over 50 SoCs with RISC-V processors. With these solutions, and professional services, Synopsys is uniquely positioned to support the RISC-V processor ecosystem.

We discuss concepts for custom extensions to the RISC-V ISA, for application-specific workloads.

The RISC-V ISA provides opcode space to encode custom instructions, typically operating on RISC-V’s register file. This can offer meaningful speedups. For higher performance, parallel processing is needed in the form of instruction-level parallelism (ILP) and data-level parallelism (DLP).

RISC-V microarchitectures may support ILP through dynamic multi-issuing. DLP can be supported with RISC-V’s vector extension (RVV). These are parallelization solutions for general-purpose computing. 

For compute-intensive workloads we propose extending RISC-V with parallel processing concepts from digital signal processors (DSPs). We propose the use of static multi-issuing on a very-long instruction word (VLIW) architecture. A 32-bit slot encodes a baseline RISC-V ISA. Additional slots encode parallel operations, possibly on vector (SIMD) units. Such VLIW/SIMD architectures preserve compatibility with the RISC-V ecosystem. They can execute existing RISC-V binary code, and can communicate with existing RISC-V peripherals.

We also discuss tools to design and program RISC-V based VLIW/SIMD architectures.