Rapid Architectural Exploration in Designing Application-Specific Processors White Paper
There are few system-on-chip (SoC) applications that do not demand higher and higher performance, combined with high energy efficiency. At the same time, SoCs have to remain flexible enough to cope with late specifications changes, post-silicon modifications, product derivatives - all to expand the revenue lifetime of an SoC. This calls for application-specific instruction-set processors (ASIPs), which combine a software programmable processor and application-specific function units with its architecture optimized for the set of functions that it has to implement. The instruction-set architecture (ISA) is tailored for the efficient implementation of the applications, while still providing enough flexibility to change the operation modes in software. The efficient implementation requires an inherent parallelism of functional units. Due to their architectural specialization, combined with instruction-level and data-level parallelism, ASIPs can offer performance and energy characteristics that are superior to general-purpose processors and close to fixed-function custom logic implementation. Due to their software programmability, ASIPs offer the flexibility required for today’s SoCs.
Architectural exploration is at the heart of any ASIP design approach. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain. We will illustrate the architectural exploration approach using a simple yet representative example.
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