Needless to say, design sizes are growing exponentially. Design complexity is increasing, and debug becomes correspondingly more complex. DTD can get you a long way in debug and will probably meet the needs of most of your debugging scenarios with at-speed trace capture. If you determine that additional signals need to be traced while performing debug with the selected DTD probes, you have the option to reconfigure the probe points, perform a fast incremental rebuild of the relevant FPGA, and run again.
Sometimes, however, you don’t know what portions of the design are active, so full signal visibility is needed. This means you require functionality that dumps the states of every register in the FPGA, with little to no overhead of FPGA resources. You then want to be able stop clocks, download all relevant register data, advance one cycle, then loop N times. FSDB processing needs to be done independently on the host, so that it does not impact runtime performance. Data expansion technology can then map the FPGA registers to the RTL source code and extrapolate all intermediate signal values. Using Synopsys ProtoCompiler GSV (Global Signal Visibility) manages these challenges, so you now have full-visibility RTL debug capability.
Designs also have multiple clocks running at different frequencies and interfaces to the real world. ProtoCompiler allows you to generate an IICE (intelligent in-circuit emulator) model and debug each clock independently.