Of course, it’s not just about achieving cycle targets or debugging software. What happens when hardware bugs occur? You need to be able to observe bugs when they happen and to be able to debug them efficiently when using an FPGA-based prototyping system. So, the challenge is to make your debug turnaround cycle fast and easy to manage, as this is often the aspect of deploying FPGA prototyping in a hardware verification flow which makes it less attractive compared to, say, emulation. Additional challenges exist around the provision of sufficient visibility into the internal workings of the design for debugging purposes.
As Joe and Bryan point out in “Deep Cycles,” you are likely running system software-based validation payloads on a scaled-out FPGA prototyping farm, and you are doing this because it is the closest approximation to actual silicon in terms of cycle throughput. Your RTL is stable. Your testing payloads are not falling over due to endless and frequent RTL bugs. You’ve already wrung out most of the hardware bugs with simulation and emulation. This leaves behind a class of bugs that, without scaled-out FPGA prototyping, are likely to only be found in actual silicon. Not good!
This trade-off between slower technologies like simulation and emulation, offering excellent visibility and ultra-fast FPGA prototyping, is where innovation helps achieve new levels of performance and debug productivity. It’s central to success in your quest to find those deeply hidden, hard-to-reach bugs.
Historically, when hardware bugs are encountered while running system software validation payloads on the FPGA prototyping platform, much effort is expended to reproduce the failures on a more debug-capable platform. This can be a difficult and lengthy process using binary chops to narrow down to a testcase that is small enough to replay on your emulation or simulation platform. The whole process can take days or weeks and is often unsuccessful. Modern FPGA prototyping platforms such as the Synopsys HAPS®-100 prototyping system change all that with high debug productivity capabilities. The ability to efficiently debug hardware problems on your FPGA platform is a huge shift and a time saver for FPGA prototyping as a hardware verification platform.