ASIP Designer comes with a rich set of example processor models provided in source code, which serve both as a modeling reference as well as a starting point for customer designs.
In previous issues of the eUpdate Newsletter we already covered the subject of data-level parallelism and instruction-level parallelism, including the corresponding example models. In this issue we will look at example processor models that demonstrate how to do a fast context switch. These models share as a common feature that registers are duplicated per context. This duplication makes it possible to quickly switch from one thread of execution to another. The motivation for requiring a fast context switching mechanism can be diverse, but broadly speaking we can make a distinction between
Fast context switching upon an interrupt, or
Switching between the multiple contexts in a multi-threaded processor
Before entering into these cases, let us look at how we can model a processor that has multiple register contexts. In the nML model, only one set of registers is declared. These registers are used to define the instructions. In nML, additional copies of a register, sometimes called shadow registers, can easily be created by adding the additional_register_contexts property to the processor model. Assume that a processor has a register file R and single field register SP, then the following property will result in the automatic creation of three shadow registers for both R and SP, thus creating a total of four contexts:
additional_register_contexts : 3 ;
If for certain registers, we want to keep a single copy that is shared by all contexts, we must add the following exclude property:
exclude_from_additional_register_contexts : SP ;
Once the multiple register contexts have been created, we must decide how to switch from one context to the next. Using Figure 1 below for reference, we will look at different ways to generate the context select signal that steers the context multiplexor CM.