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ASIP eUpdate, April 2015
Overview
Welcome to the latest issue of the ASIP eUpdate Newsletter, our bi-annual publication to keep you informed on topics related to application-specific instruction-set processor (ASIP) design. ASIPs are processors with an architecture and instruction set tuned for a specific application domain. They rely on similar techniques as used in the design of hardware accelerators to reach high performance and low power: heavy use of parallelism and specialized datapath elements. Yet ASIPs retain software programmability within their application domain, resulting in C/C++ programmable processors and accelerators with the lowest power possible.
March 2015 has been a milestone for Synopsys’ ASIP activities, with the announcement of ASIP Designer™, which we will cover in this newsletter. You will also learn about, customer successes and upcoming events, and find other resources to help you design your application-specific processors for your specific requirements.
Introducing ASIP Designer
On March 25th, Synopsys announced the availability of ASIP Designer, which automates the design of application-specific instruction-set processors and programmable accelerators. The new tool leverages the proven technology of IP Designer and Processor Designer*, which have been used by more than 50 companies to design hundreds of successful products.
ASIP Designer’s patented technology offers the following features:
- Modeling of ASIP instruction-set architectures in the nML processor description language. Next to nML, the ASIP’s periphery can be modeled in cycle- and bit-accurate C code
- Unique compiler-in-the-loop™ technology, enabled by the automatic generation of a comprehensive software development kit (SDK) for each ASIP modeled in nML, containing
- An optimizing compiler
- A fast instruction-set simulator
- A flexible (multicore) debugger
- Multi-faceted profiling capabilities
- Automatic generation of a power and area efficient hardware implementation of each ASIP in synthesizable Verilog or VHDL.
- Multi-faceted verification capabilities, including the automatic generation of ASIP-specific test programs in C and assembly code.
ASIP Designer comes with a wide range of example ASIP designs for highly differentiated architectures including 16 and 32 bit microcontrollers, DSP cores featuring vector processing and SIMD support, VLIW architectures and more, all provided in nML source code. These allow designers to quickly start designing their own ASIP that targets their specific application requirements.
For more detailed information about ASIP Designer features and capabilities, go to the product web page and download the brochure and data sheet or contact us.
*IP Designer originated from Target Compiler Technologies and Processor Designer originated from CoWare
Technology Feature: Architectural Exploration
ASIPs close the gap between highly optimized fixed-hardware data path implementations and standard processor IP. Efficient architectural exploration is fundamental to the ASIP design process, as it helps identify the best-suited processor architecture in a given amount of time.
Synopsys’ ASIP Designer provides all the ingredients for efficient architectural exploration. View the webinar and read the whitepaper to see how architectural exploration capabilities are central to an efficient ASIP design methodology. A motion estimation algorithm example is used to describe the flexibility of an ASIP approach and the efficiency of the tool-assisted architectural exploration approach, starting from a RISC-like architecture and eventually resulting in a highly specialized processor architecture that applies both instruction parallelism as well as data parallelism.
White paper: Rapid Architectural Exploration in Designing Application-Specific Processors
Customer Story: Conexant
On March 23rd, 2015, Conexant presented a paper at SNUG Silicon Valley entitled “Design of Application-Specific Processor for Far-field Voice Processing”. In his presentation, Ragnar Jonsson discussed why they decided to use an ASIP, how to design an ASIP using dedicated tools, and how Conexant were able to design their new audio processor in about six months and had the final version within one year. (A SolvNet account is required to access the paper).
Application Notes
Application notes are highly appreciated by engineers to leverage other people’s expertise in using the tools. The following application notes are available in SolvNet (a SolvNet account is required to access the app notes):
- Application Note: Designing a Programmable FFT Accelerator with ASIP Designer, addressing the design of a programmable accelerator block for Fast Fourier Transform (FFT). By creating an ASIP featuring clever addressing modes, a powerful and compact, yet software-programmable design is obtained that can execute different types of FFT algorithms.
- Application Note: Design of an MPSoC for JPEG Compression with ASIP Designer, addressing the design of a programmable heterogeneous multicore architecture for high throughput JPEG image compression.
- Application Note: Register-Transfer Level Low-Power Optimizations for ASIPs, discussing ASIP-specific low-power optimizations made at the register-transfer level. It shows that applying these techniques in the automatic generation of RTL models can reduce dynamic power dissipation by a factor of two to three
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Events