Formality

Highest Verifiable QoR with Design Compiler and Fusion Compiler

Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable.

Formality supports all Design Compiler® and Fusion Compiler™ optimizations and provides the highest quality of results (QoR) that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs.

Implementing manual ECO’s is made easier with  the interactive ECO functionality in Formality. Designers are guided through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes. These capabilities help designers reduce turn-around-time (TAT) implementing late-stage ECOs resulting in shorter, more predictable schedules.

...it's a lot of fun to work through each logic cone..."

Sathappan Palaniappan, Prinicpal Engineer

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Broadcom

At Silicon Valley SNUG 2019, Broadcom presented a paper on their success implementing manual ECO’s with Formality’s interactive ECO functionality. Listen to Sathappan Palaniappan, Principal Engineer at Broadcom briefly describe his experience using Formality for manual ECO’s and the highlights from his presentation. Links to the SNUG paper and presentation are provided at the end of the video.

Benefits

  • Highest verifiable QoR with Design Compiler and Fusion Compiler
  • Intuitive flow-based graphical user interface
  • Verifies low-power designs including power-up and power-down states
  • Advanced debugging and interactive ECO capabilities reduce manual ECO TAT
  • Multicore verification boosts performance
  • Verifies full-custom and memory designs when including ESP technology