Formality supports all Design Compiler® and Fusion Compiler™ optimizations and provides the highest quality of results (QoR) that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs.
Implementing manual ECO’s is made easier with the interactive ECO functionality in Formality. Designers are guided through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes. These capabilities help designers reduce turn-around-time (TAT) implementing late-stage ECOs resulting in shorter, more predictable schedules.