ASIP eUpdate, February 2023

<p>Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.</p><p>This bi-annual newsletter provides you with easy access to ASIP-related resources.</p>

ASIP Designer

Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.

This bi-annual newsletter provides you with easy access to ASIP-related resources.

Technology Feature: Ease-of-use improvements in the ChessDE Graphical IDE

In the T-2022.06 and U-2022.12 ASIP Designer™ releases and their ASIP Programmer™ derivatives, several enhancements have been added to the ChessDE graphical IDE to improve the user experience and increase productivity. These enhancements include easier context-aware navigation in the editor, various new visualization capabilities in profiling, and more user-friendly feedback of the compiler’s scheduler.

ChessDE editor: Context-aware navigation based on a language server protocol (2022.06)

ASIP Designer and ASIP Programmer now include a language server that provides language-specific smart features for C/C++ application code. The ChessDE GUI can communicate with this server through a specific language server protocol.

Once this feature is enabled in the ChessDE preferences menu, the context menu of the editor then contains an additional submenu Language server, as shown in Figure 1. This menu allows the user to quickly navigate through the source code to the declarations, definitions, or implementations of the current symbol, get detailed information on it, or speed-up editing via auto-completion of existing symbols.

Figure 1: Trv family of processor models

Figure 1: ChessDE editor using a language server protocol

Visualizing profiling results: Bar charts and flamegraphs (2022.06)

The ChessDE profiler now includes cycle bar charts in call-tree tables, which helps identify the most time-consuming parts of a program more quickly. An example is shown in Figure 2.

Figure 2: Cycle bar charts in call-tree table

As an even more concise and intuitive visualization of this information, ChessDE is now able to generate flamegraphs, as shown in Figure 3.

Figure 3: Example flamegraph (bottom) and corresponding configuration options (top)

The vertical axis contains the call tree information. Functions in lower rows are deeper in the call tree. The horizontal axis represents the time spent in each function in the call tree as a fraction of the total execution time.

Flamegraph information can be exported in xml format and hence be used as a reference to be compared against, to explore the effect of an architectural change. If a reference XML file is specified, the tool generates a differential flamegraph as shown Figure 4. A function that performs better with respect to the reference would be colored blue, a function that became slower is colored red.

Figure 4: Differential flamegraph

Visualizing profiling results: Cachegrind (2022.06)

ChessDE now supports the export of profiling data in the Callgrind profile format. The resulting file can then be visualized using Cachegrind, an open-source tool that users can install separately from ASIP Designer. On most Linux platforms, it is available as KCachegrind. There is also a Windows port known as QCachegrind.

Figure 5 shows the configuration of profiling data in ChessDE (bottom left), and the resulting Cachegrind visualization of the function profile (top left), call graph (top right), and highlighted source and assembly code (bottom right). 

Figure 2: Instruction formats supported by Trv<x> processor models (visualization by ASIP Designer's nMLView tool)

Figure 5: Visualization of ASIP profiling information in Cachegrind

Compiler: enhanced, user-friendly feedback on instruction scheduling (2022.12)

The compiler’s optional scheduling reports have been enhanced by showing the actual assembly syntax and the involved registers of the scheduled instructions. This enables developers to better link scheduler feedback to the nML processor model, without having to dive deep into the internal representation of operations in a scheduling graph. This applies to the textual scheduling reports as well as to their graphical representation, an example of which is shown in Figure 6.

Figure 3: Tmoby ASIP architecture, with RISC-V scalar data-path (far left) and vector data-path extensions

Figure 6: Visualization of a scheduling graph

What’s New: ASIP Designer T-2022.06 and U-2022.12 Releases

Since the last edition of this newsletter, we have launched two new feature releases of ASIP Designer, in June 2022 and December 2022, providing various enhancements and extensions. The following is an extract of accumulated enhancements from both releases, sorted by categories (customers can refer to the official Release Notes for a comprehensive list). 

Click on each tab for additional information about that new feature

Example Processor Models

Designers can choose from an extensive library of example processor models provided as nML source code. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration and customer-specific production designs. In the 2022.06 release there have been following updates: 

  • All models of the Tvliw family have been unified and cleaned up. The modeling concept of “nML components” is used for all variants (2022.06).
  • The Tcom8 example model has been enhanced with vectorized matrix multiplication (2022.06).

Processor Modeling

  • Support for vectors of struct types in the PDG modeling language (2022.06)
  • Hierarchical instantiation of IO modules inside other IO modules and IO interfaces (2022.12)

C/C++ Compiler

ASIP Designer comes with a unique and patented compiler solution, with the compiler automatically retargeting itself to the processor architecture. This eliminates any need for compiler backend customization by the user. Releases 2022.06 and 2022.12 offer the following enhancements: 

  • Improved modulo scheduling of leaf loops by exploiting multiple priority functions, resulting in better schedules and shorter run times (2022.06).
  • The LLVM-based front-end has been updated to the more recent LLVM version 14.0 (in 2022.06) and further to LLVM version 15.0 (in 2022.12).
  • The compiler scheduling feedback (reports and graphs) has been improved to show the assembly syntax instead of the internal operation names (2022.12). More details can be found in the Technology Feature section in this eUpdate.
  • More robust support for software stacks in memory. Specifically, an indirect addressing scheme based on a “roving pointer” is introduced as a fallback, when the spill area outgrows the stack pointer immediate offset range (2022.12).


ChessDE GUI, Instruction-Set Simulation and Debugging

  • The ChessDE editor has been enhanced to use a language server, allowing context aware editing and navigation in C/C++ source code (2022.06: LLVM frontend only, 2022.12: full support). More details can be found in the Technology Feature section in this eUpdate.
  • The ChessDE debugger has been integrated with external profiling and visualization tools like Flamegraph, Cachegrind, and Gprof (2022.06). More details can be found in the Technology Feature section in this eUpdate.
  • Uniform approach to set-up and run a test in GUI/console/client mode, using Run/Debug configurations (2022.12).
  • Support for on-the-fly profiling (without postprocessing a file) (2022.12).
  • Support for source-code coverage reporting in Lcov’s .info format (2022.12).

RTL Generation, Verification, and Synthesis Support

  • Refined generation of ASIPs in dual-core lockstep (DCLS) configuration, with adapted synthesis scripts (2022.06), targeting designs with functional safety or security requirements.
  • Any hierarchical module in the ASIP’s RTL implementation can be specified for automatic duplication in a lock-step configuration (2022.12). 
  • PDG hierarchy is kept in the generated Verilog RTL implementation (2022.12).

Additional Resources

Customer References