Explore ASIP tutorials

Tmotion – An ASIP Designer Demonstration

English

In this tutorial we give a once-over-lightly tour of ASIP Designer’s compiler-in-the-loop™ and synthesis-in-the-loop™ design methodology showing the tool at work, by the example of successively building an accelerator for a motion estimation application. Starting from a plain RISC microprocessor, in five design steps we gradually extend the architecture by adding specialized instructions, data-level parallelism and instruction-level parallelism, and special-purpose memory. At each step we profile the impact on performance and area.

Tmatch – A Flexible Stereo Image Matching Accelerator Designed with ASIP Designer

English

In this video we document an advanced case study featuring the development of an accelerator for stereo image matching, while showing the tool at work. A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for this application. Stereo image matching algorithms are very demanding in respect of processing power (about 30 TMACs/s). We optimized the application code and co-developed the optimized instructions at high level. Using the compiler-in-the-loop™ flow offered by ASIP Designer we easily verified the correctness of the application code and evaluated the performance impact. Within a few weeks we explored multiple efficient implementation solutions and made performance vs. cost tradeoffs. The result of this design effort is Tmatch, a highly specialized vector ASIP with limited ILP. The ASIP features design techniques enabling the reuse of partial computed results and multiple specialized memories in parallel with specialized addressing modes.

MMSE - An Accelerator for 5G New Radio MMSE Equalization using Cholesky Decomposition

English

In this video we document an advanced case study featuring the development of an accelerator for 5G NR channel equalization, while showing the tool at work. A DLX RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for this application. 5G New Radio (NR) channel equalization algorithms are very demanding in respect of processing power (several TMAC/s), requiring a huge number of complex-number MAC operations in combination with high memory bandwidth and quite irregular memory access patterns. In this case study, customized instructions and datapaths were added to a baseline RISC design in a stepwise approach. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop™ and synthesis-in-the-loop™ optimization flows of ASIP Designer. The resulting design is a highly specialized ASIP featuring custom instructions, data level parallelism (SIMD), instruction level parallelism (ILP), and multicore context, which optimally balances the datapath with the memory bandwidth, and the SIMD size with the number of cores.