Cloud native EDA tools & pre-optimized hardware platforms
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In this tutorial we give a once-over-lightly tour of ASIP Designer’s compiler-in-the-loop™ and synthesis-in-the-loop™ design methodology showing the tool at work, by the example of successively building an accelerator for a motion estimation application.
Starting from a plain RISC microprocessor, in five design steps we gradually extend the architecture by adding specialized instructions, data-level parallelism and instruction-level parallelism, and special-purpose memory. At each step we profile the impact on performance and area.