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In this video we document an advanced case study featuring the development of an accelerator for stereo image matching, while showing the tool at work. A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for this application.
Stereo image matching algorithms are very demanding in respect of processing power (about 30 TMACs/s). We optimized the application code and co-developed the optimized instructions at high level. Using the compiler-in-the-loop™ flow offered by ASIP Designer we easily verified the correctness of the application code and evaluated the performance impact. Within a few weeks we explored multiple efficient implementation solutions and made performance vs. cost tradeoffs. The result of this design effort is Tmatch, a highly specialized vector ASIP with limited ILP. The ASIP features design techniques enabling the reuse of partial computed results and multiple specialized memories in parallel with specialized addressing modes.