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In this video we document an advanced case study featuring the development of an accelerator for 5G NR channel equalization, while showing the tool at work. A DLX RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for this application.
5G New Radio (NR) channel equalization algorithms are very demanding in respect of processing power (several TMAC/s), requiring a huge number of complex-number MAC operations in combination with high memory bandwidth and quite irregular memory access patterns. In this case study, customized instructions and datapaths were added to a baseline RISC design in a stepwise approach. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop™ and synthesis-in-the-loop™ optimization flows of ASIP Designer. The resulting design is a highly specialized ASIP featuring custom instructions, data level parallelism (SIMD), instruction level parallelism (ILP), and multicore context, which optimally balances the datapath with the memory bandwidth, and the SIMD size with the number of cores.