Designing ASIPs with Confidence: A Perspective on the Verification of Application Specific Instruction Set Processors
Well-designed ASIPs with a strong SDK combine C/C++ programmability with the power and performance of dedicated hardware. Product families based on ASIP platforms are often highly flexible, capable of addressing multiple market segments with the same silicon and handling updates in the field. They lean well towards software-driven verification with few penalties for late product requirement changes or fixes.
ASIP Designer offers an automated, coverage-driven processor verification flow. It is well structured and documented, including source code examples. The flow augments dynamic tests with formal design checks. Designers and verification teams using ASIP Designer find its verification flow effective, efficient, and well-integrated into their existing high-level and RTL test processes. They tape out with confidence.
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