RSoft & Photonic Solutions Newsletter

May 2019

Quick Tip: Photonic LVS Feature in Synopsys PIC Design Suite

Layout-Versus-Schematic (LVS) checks are the final phase of the PIC verification process and provide a high degree of confidence in the functional correctness of the physical database. However, LVS checks will not detect a poor implementation and cannot differentiate, for example, between a good ground bonding scheme and an ineffective one. During the library QA stage, the LVS runset is configured to run as optimally as possible, but even so it is highly likely that extraction errors will still be reported.

Tip: Be prepared to discern real issues from false issues, and to provide justification for any waivers.

The PIC Design Suite’s LVS feature provides a high degree of confidence in the physical database. It works as follows:

  • Optsim Circuit is used for schematic capture and simulation. It generates a SPICE file describing the intended functional design.
  • OptoDesigner is used to finalize (or create from scratch) the layout.
  • OptoDesigner always annotates the GDSII file with nodes describing bounding boxes, parameters, and ports of devices, which are normally invisible to the tool-chain.
  • The LVS feature extracts these nodes and:
    • Creates a connectivity graph based purely on the node content, allowing the user to visualize the netlist.
    • Creates an annotated GDSII file, in which each device is given an overlay cell containing marker layers for device type (+parameters) and ports.
    • Creates a runset script file for ICV, allowing ICV to validate the netlist it extracts from the layout to the input Spice file. Optionally, ICV is run from inside the tool.

References:

  1. https://www.synopsys.com/designware-ip/technical-bulletin/guidelines-for-integration.html
  2. https://www.synopsys.com/photonic-solutions/pic-design-suite.html

RSoft Application: RSoft BeamPROP Simulations for Mode Spatial Division Multiplexing

Spatial Division Multiplexing (SDM) for optical fiber transmission is useful for overcoming the capacity limit of wavelength division multiplexing. SDM increases the spectral efficiency per fiber by multiplexing the signals in orthogonal LP modes in few mode fibers (FMF) and multi-core fibers. In SDM systems, the mode multiplexer/demultiplexer (MUX/DEMUX) is a key component because it equalizes the mode-dependent loss, compensates for differential mode delays, and is used to construct transceivers. Different types of mode MUX/DEMUX have been proposed in recent years. RSoft BeamPROP is a great tool to model and design mode MUX/DEMUX.

This note will introduce the simulations for two proposed mode MUX/DEMUX structures for FMF. The first structure is a compact mode multiplexer using a 3D silicon-rich silica waveguide on a silicon chip, based on a paper by Hiraki et al.1 It can demultiplex three modes with an approximate 0.6mm^2 chip area. The second structure is a PLC-based asymmetric parallel waveguide to realize the mode conversion function by matching the effective indices of the LP01 and LP11 modes, based on a paper by Hanzawa et al.2   The design files can be accessed in the RSoft product section on the Customer Support Portal.

On-Chip Integrated Silica MUX/DEMUX

Figure 1 shows a schematic of an on-chip-integrated mode multiplexer. The input from the FMF excites a set of symmetric supermodes. Symmetric modes evolve into distorted supermodes through an adiabatic tapered waveguide. Distorted supermodes are coupled into isolated ports, and then coupled into individual SMFs.

We have set up this structure in the RSoft CAD, as shown in Figure 2. Pathway monitors are used to measure the insertion loss. Spatial monitors are used to record the field at different locations. Figure 3 shows the propagation behaviors with three LP modes incident in the waveguide and their insertion loss along the propagation direction. Figure 4 shows field patterns at output ports and their insertion loss and crosstalk. Note that the structure setup is not completely identical to the one presented in the paper by Hiraki et al.1

Figure 1. Schematic of on-chip-integrated mode multiplexer

Figure 2. Layout in RSoft CAD and index profile at the beginning and the end

Figure 3. The propagation field and the insertion loss along the structure

Figure 4. The field pattern and power output at each output ports corresponding to different input mode

Asymmetric Mode Coupler (AMC)

As shown in Figure 5, a PLC-based asymmetric mode MUX/DEMUX can be realized by matching the effective indices of the LP01 and LP11 modes of two waveguides with different widths. The LP01 mode from port 2 is converted to the LP11 mode in waveguide 1 and output at port 3, and the LP01 mode from port 1 is output directly at port 3. Thus, the LP01 and LP11 modes are multiplexed at port 3. The AMC can also be used as a mode DEMUX because the coupler has a symmetric property.

Figure 5. Schematic of proposed asymmetric PLC mode coupler

Figure 6 shows the Neff for the fundamental mode and the first-order mode versus the waveguide width generated with an RSoft MOST scan. The Neff for the first-order mode matches with the fundamental- mode at different waveguide widths. If the coupler is configured at these two widths, then the fundamental mode of the narrower waveguide will be coupled into the first-order mode of the wider waveguide by the phase-matching condition.

Figure 6. Neff versus width of waveguide for fundamental and first-order modes

Figure 7 (a) The AMC structure setup in RSoft CAD; (b) Coupling power versus coupling length

Figure 7 shows the AMC structure setup in RSoft CAD and the optimal coupling length from one mode to another generated with a BeamPROP simulation. With this optimal coupling length, Figure 8 shows how beam propagates with different incident conditions: LP01 mode of the narrower waveguide incident on Port 2; the LP02 mode of the wider waveguide incident on Port 1; and the equal power of two modes incident on Ports 1 and 2, respectively.

Figure 8. BPM simulations with different input conditions

The bandwidth, polarization dependence, and crosstalk (the power in the unwanted mode) can be obtained by scanning versus wavelength, as shown in Figure 9. This device can reach to 490 nm wide bandwidth with 0.005 dB polarization dependence and -28 dB crosstalk.

Figure 9. Device performance simulation results for bandwidth, polarization dependence, and crosstalk

References:

1.      Hiraki, T., Tsuchizawa, T., Nishi, H., Yamamoto, T., & Yamada, K. “Monolithically integrated mode multiplexer/de-multiplexer on three-dimensional SiOx-waveguide platform”, Optical Fiber Communication Conference (pp. W1A-2). Optical Society of America. (2015, March).

2.      Hanzawa, N., Saitoh, K., Sakamoto, T., Matsui, T., Tsujikawa, K., Koshiba, M., & Yamamoto, F. “Two-mode PLC-based mode multi/demultiplexer for mode and wavelength division multiplexed transmission” ,Optics Express21(22), 25752-25760 (2013).

PIC Training

Don't forget! PIC training at the University of Rochester takes place this month, May 14th-17th. Synopsys and the University of Rochester, NY present a four-day training on photonic design for photonic integrated circuits (PICs).

The training is for academic and industry attendees interested in understanding the development of PICs and the role of software automation in their design, simulation, and fabrication procedures.

Training participants will receive an overview of the integrated photonics eco-system, together with an introduction to Synopsys PIC Design Tools and their role in integrated photonics design and manufacturing.

This training will feature live demonstrations and a hands-on session using Synopsys tools for PDK-driven PIC design. During the hands-on session, attendees will have the opportunity to work directly with the software under the guidance of expert technical staff from Synopsys.

Calendar of Events

For the latest event calendar, please go to our Events page.