One of the most important, yet often overlooked, sources of information to the layout engineer is the set of integration notes for the various IP blocks that will be incorporated into the chip. In many cases, these are provided as PDF data books, however they may also be simple text documents or release notes.
Tip: It is vital to ensure that all delivered documentation is retained, and is scanned for important integration requirements, guidelines, or tips.
Obvious things to look for are ESD requirements, guard-bands, blockages and other place/route rules. However, less than obvious are the recommended settings for physical verification tool rule sets, results from the vendor’s own verification tests (including DRC waivers), and specific layer usage and mapping requirements. This is all highly useful information that helps ensure a trouble-free integration.