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In times of economic or political uncertainty, all businesses look for ways to reduce costs while increasing revenue. It also becomes more critical than ever to accurately predict the cost of the chip design projects to ensure a good return on investment (ROI). This post discusses chip design cost factors to keep in mind when setting a budget and provides advice for reducing expenses.
Every chip design project is unique, but five basic factors contribute to the overall cost.
1. Content Libraries
Content libraries consist of the third-party IP used in a chip design project, including common functions, input and output (I/O) circuits, and on-chip memory. A content library license fee varies but can range into tens of millions of dollars. Firms must also pay per-chip royalties, which should be factored into the project budget.
Electronic design automation (EDA) tools are used to lay out circuits virtually, simulate operations, and verify performance. EDA software comes in various forms, including on-premises, cloud-hosted, and software as a service (SaaS). Pricing may be license-based, usage-based, or a combination of the two. In addition, EDA tools require powerful computers and a lot of storage capacity, which means investing in on-premises or cloud infrastructure.
3. Foundry Manufacturing
The foundries that manufacture chips charge per silicon wafer. The smaller a chip is, the more chips an organization can get per wafer. However, other design costs, such as R&D, get higher as the chip size gets smaller. Controlling chip design cost means finding the balance between efficient wafer usage and realistic R&D.
The faster a product makes it to the market, the better the overall ROI of the project. In addition to the time spent designing the chip, firms must factor in the lag time between tape-out and foundry production. Every design has bugs that must be ironed out between designers and the foundry before production begins.
The final step before production involves projecting the demand for the new chip and committing to orders with the foundry. This is a complex and high-risk operation. If you order too few chips, you’ll have a supply shortage and potentially lose sales; if you order too many, you could waste thousands or even millions of dollars on the unused stock.
Some chip design cost factors are unavoidable or difficult to reduce. Content libraries, for example, are included in nearly every chip design project, even if the firm has developed some of its own IP. Other costs, however, can be minimized by utilizing cloud tools and resources.
Cloud computing can reduce many expenses involved in chip design. For example, cloud-native EDA solutions use elastic scaling that automatically grows and shrinks to meet demand, so you never have to pay for instances you aren’t using. Cloud EDA tools running on a cloud-based HPC (high-performance computing) cluster can perform highly accurate simulations, helping to minimize defects and reduce the time between tape-out and production. An all-in-one SaaS EDA solution, such as Synopsys Cloud, eliminates the need to purchase or maintain on-premises infrastructure for chip design workloads.
Synopsys is the industry’s largest provider of electronic design automation (EDA) technology used in the design and verification of semiconductor devices, or chips. With Synopsys Cloud, we’re taking EDA to new heights, combining the availability of advanced compute and storage infrastructure with unlimited access to EDA software licenses on-demand so you can focus on what you do best – designing chips, faster. Delivering cloud-native EDA tools and pre-optimized hardware platforms, an extremely flexible business model, and a modern customer experience, Synopsys has reimagined the future of chip design on the cloud, without disrupting proven workflows.
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