Since CDC-clean is a must-have for release signoff, the time and effort consumed to achieve this is non-trivial and must be fully accounted for in the product development lifecycle. Of course, the effort to achieve this will scale with design size. A modern multi-billion-gate ASIC, with hundreds of clocks and potentially millions of CDC clock crossings, might take days of compute time and require terabytes of memory to run a full-chip, flat-level CDC analysis. Turnaround time can be a significant issue here. What can be done about that?
Firstly, as with everything in the development of large ASICs, you need to take a divide-and-conquer approach. A hierarchical, bottom-up approach allows you to run CDC analysis one block at a time, just as you would for synthesis and static timing analysis. This way, CDC analysis can shift-left to earlier stages of the development flow, with an iterative approach to cleaning CDC issues as you go, block by block, and not leaving CDC analysis to be done just before release when fixing CDC bugs can be costly and disruptive. Then, as you move up to the next level of hierarchy, you can substitute the cleaned blocks with abstract CDC models, containing only the clock paths that are relevant to the next level of integration, and abstracting away all internal-only clock crossing paths. When that sub-system is CDC-clean, do it again at the next level of hierarchy, and so on. Synopsys VC SpyGlass® CDC supports an efficient hierarchical approach with the CDC signoff abstraction model (SAM) flow, which can yield 3x or greater turnaround time improvements with multi-factor reductions in memory requirements with no degradation of quality of results (QoR).