At the lower end of the IO density spectrum, and with fewer die-to-die connections, is the organic substrate. This 2D type of standard packaging is relatively inexpensive and well established in the semiconductor industry. Because it lacks the fragile microbumps of its 2.5D and 3D counterparts and due to the maturity of the processes, organic substrate packaging tends to have higher yields. There are testability functions (with low-cost wafer-level screening for known good die), but there’s no requirement for test and repair of faulty connections.
Organic substrates are also marked by good heat dissipation, low warpage, and large SiP integration without reticle limitations.
Redistribution Layer (RDL) Fan-Out
Not yet in widespread use, the relatively new RDL fan-out packages provide a density that is similar to that of the silicon interposer but at less complexity and lower cost. Fan-out is an advanced packaging type that assembles one or more dies, leading to better performance and more IOs for a variety of IoT, networking, and computing applications. RDLs, consisting of copper metal connection traces, connect one part of a package to another electrically. In an RDL fan-out package, the RDL traces can be routed inward and outward; this allows for thinner packages with more IOs.
In a silicon interposer, a connectivity die called an interposer is implemented in silicon to connect two dies. This 2.5D type of packaging allows for dense connectivity using microbumps, a vertical interconnect technology for stacked dies. Because of the complex assembly of this packaging type, as well as the delicate nature of microbumps, there are more associated yield issues. Packaging vendors address this through quality assurance measures as well as test and repair mechanisms in the die-to-die interface. Silicon interposers boast thousands of lines in parallel, and these lines are designed with logic to test connectivity, determine whether there’s a break, and reroute when needed. For example, if an interface has 1,000 lines, you’d design a PHY for 1,100 lines, providing 10% redundancy to allow for rerouting in the case of failures. However, with silicon interposers, it is difficult to screen wafers for known good die. In addition, this package type has reduced thermal dissipation and its interposer size is limited to the mask reticle size.
A type of 3D stacked packaging, hybrid bonding delivers the highest density along with power efficiency. There are through-silicon vias (TSVs) for connectivity. With two wafers bonded together and working as one, there’s no wasted power when driving the channels and power of each IO can be reduced as needed. Compared to interposers, hybrid bonding does present greater complexity and cost. It’s ideal for applications like AI training engines, which need substantial processing capabilities along with low latency. Stacking memory over the processor in a hybrid bonding package provides the performance and latency needed.