Traditional data centers are built with CPUs or, in some cases, a mix of CPUs, GPUs, and specialized ASICs. For hyperscale data centers—which are designed to scale up quickly and in a massive way to support HPC applications—these types of chips are not sufficient. Their high volumes of data demand the powerful processing that’s been found in larger chips. Cerebras, for example, is noteworthy for developing the Wafer-Scale Engine (WSE), the biggest chip ever built. Designed for deep-learning systems, the Cerebras WSE provides the compute, memory, and communication bandwidth to support dramatically faster and more scalable AI research compared with traditional architectures.
However, going big with monolithic dies—and at advanced nodes, no less—is an expensive endeavor and may not result in the most optimal yield. To alleviate the costs as well as yield issues as chip sizes approach full reticle size, designers are choosing multi-die chip architectures. In a multi-die chip architecture, SoCs are partitioned into smaller modules, also called chiplets, in advanced multi-chip packaging. Compared to a monolithic design, where all of the functionality is on a single piece of silicon, this disaggregated approach provides economic benefits from a yield standpoint and also the product modularity and flexibility to mix and match functional blocks in separate chiplets to address different market segments.
Connected by die-to-die interfaces, the chiplets can be placed side by side, which is the prevalent and lower cost approach. Or, the blocks can be assembled in a 2.5D or 3D package to allow even greater density. High-bandwidth memory (HBM) designs, which consist of large 3D stacked DRAM integrated on the SoC, are one of the increasingly popular applications driving the move to 3DICs.