Cloud native EDA tools & pre-optimized hardware platforms
Synopsys and Lund University, Sweden, held the ASIP University Day 2019, an informal workshop to learn more about the exciting options ASIPs offer, and what it takes to develop them.
Application-specific instruction set processors (ASIPs) have established themselves as a third implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as 5G, data centers, artificial intelligence, and automated driving assistance have fueled the development of such ASIPs, and triggered many university projects. Processor design projects such as the RISC-V initiative at UC Berkeley have also generated a lot of interest in designing specialized, application-optimized processor architectures.
Used by top tier companies for hundreds of successful projects to date, Synopsys’ ASIP Designer™ is the market leading tool for the design, verification and programming of ASIPs.
On September 25th, Synopsys, in cooperation with the Department of Electrical and Information Technology of Lund University organized the ASIP University Day 2019. Leading university teams presented results from their ongoing ASIP projects in domains such as 5G baseband and AI accelerators. Synopsys presented latest case studies and in-depth insight into the ASIP Designer technology. Teaching embedded processor design classes, and how to leverage ASIP Designer, was another subject of the day.
|8:30 - 9:00||Registration|
|9:00 - 9:40||Getting started … Application-Specific Processors (ASIPs) in System-on-Chip Design: Market and Technology Trends
Markus Willems, Synopsys
ASIPs have established themselves as an implementation option next to standard processors IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability. This talk will provide an introduction into Synopsys' ASIP Designer tool-suite, targeted markets, business models, and how Synopsys collaborates with university partners in this domain.
|9:40 - 10:20||Modern and Future Communications: Dealing with High Variability of Handset Workloads and Scalable Algorithms
Farhan Moin, TU Dresden
During this session we present the necessary capabilities of a vector DSP implementation to efficiently process a highly scalable GFDM waveform algorithm in the context of 5G and beyond use cases. We investigate structural properties and numerical precision of the GFDM algorithm, propose a scalable vectorised approach for single instruction multiple data processing, and carry out a performance-cost evaluation using the ASIP Designer Tool Suite. The presentation covers our key findings to enable GFDM functionality on handheld user equipment.
|10:20 - 10:40||Coffee Break|
|10:40 - 11:20||ASIP Designer Example Models – Starting Point for Your Next Project
Rik De Wulf, Synopsys
ASIP Designer comes with an extensive library of example models, with each release providing additional models and enhancements. These example models ship as nML source code and illustrate how to model certain features, but also serve as a starting point for your own ASIP design. The library includes standard RISC architectures including implementations of the RISC-V ISA plus extensions, wide-vector SIMD architectures, VLIW examples illustrating instruction-level parallelism, as well as specialized accelerators. During this session we will provide an overview of this library, and will drill into details for selected example models that have recently been added to the library.
|11.20 - 12:00||Extending RISC-V IPs for efficient computation of data analytics algorithms: the ETH Zurich research and teaching experience Pasquale Davide Schiavone, ETH Zuerich
Near-sensors computation is revolutionizing the "Internet-Of-Everything" (IoE) by bringing more efficiency to the connected objects and thus enabling denser and more performant network to analyze data. At the Eidgenoessische Technische Hochschule Zuerich (ETH Zurich) and University of Bologna, the open-source parallel ultra low power (PULP) project aims to cope with the IoE challenges by developing an optimized processor based multi-core platform operating in near-threshold. The open-source RISC-V ISA is chosen as basis to develop our processors due to its native support for custom extensions, which the PULP cores heavily leverage to increase the energy-efficiency of IoE applications. Synopsys’ ASIP Designer is contributing to our activities about the newest extensions for our cores and for teaching activities thanks to its efficient design flow that makes the exploration and evaluation faster.
|12.00 - 12:40||Massive MIMO Baseband ASIP with Parallel Memory and Decoder Accelerator
Mohammad Attari, Lund University
Our massive MIMO baseband ASIP implementation, equipped with SIMD processing capabilities and a systolic array baked right into the processor pipeline, is further enhanced by utilizing the instruction compaction technique in order to reduce the memory footprint. In addition, work is ongoing to further customize the design by including a parallel memory specially designed to cater to the specific memory access requirements of MIMO processing, and also a polar decoder accelerator in RTL format.
|12:40 - 13:40||Lunch|
|13:40 -14:20||ASIP Acceleration for FFT Processing in Wireless Communication and Radar Sensing
Werner Geurts, Synopsys
FFT is an efficient algorithm for computing discrete Fourier transforms. It has many applications, in wired and wireless communication, in radar sensing, in speech and audio processing. In this session we will focus on applications that require a high sample rate. More specifically, we will look at real time FFT implementations for wireless communication and for radar sensing. For these high sample rates, real time and area as well as power efficient implementations can be realized by means of application specific processors. Such processors combine FFT-specific operations and addressing modes with instruction and data-level parallelism.
|14:20 - 15:00||Exploration of Memory Energy-Reduction Strategies for a Deep Learning ASIP
Lennart Reimann, RWTH Aachen
Convolutional neural networks (CNNs) are more and more used in many applications on embedded systems. But it should be noted that CNNs are subject to high computational efforts, which require a large amount of data to be stored on off-chip memories, mainly DRAMs. The energy consumption is often an important factor for embedded systems. Thus, strategies are required to mitigate the energy consumption of the system, especially for the highly energy consuming DRAM. In this work, suitable approaches aiming to reduce the energy consumption of the DRAM for a CNN ASIP are implemented and examined, e.g. the reduction of data transmissions.
|15:00 - 15:30||Coffee Break|
|15:30 - 16:10||ASIP Acceleration for Cryptography and Security Applications
Werner Geurts, Synopsys
Many embedded applications rely on cryptographic and hashing algorithms to transmit and to store data in a safe way. Examples are wired and wireless communication and solid state storage. In these contexts, the coding, decoding and hashing of data has to be executed at the rate with which the data is transmitted over a channel or stored to a solid state memory. At these high rates, application specific processors are an efficient way to implement the cryptographic and hashing algorithms. In this session, we will look at how standard algorithms such as AES, RSA and SHA can be accelerated by combining custom data paths, register and memory structures with instruction and data level parallelism.
|16:10 - 16:50||A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet
Robert Wittig, TU Dresden
Tactile Internet as an evolution of the Internet of Things (IoT) will enable real-time interactive applications in industry and society. It requires low latency and security. Security comprises encryption and data authentication. Digital signatures enable the latter. With the rise of quantum computers, most currently employed digital signature schemes will become unsecure. One promising post-quantum secure algorithm is the eXtended Merkle Signature Scheme (XMSS). It is computationally expensive and thus contradicts low latency requirements. We proposes a latency-optimized ASIP accelerator for hash-based digital signature processing for the XMSS algorithm. Our architecture improves the latency of signing and verification into the sub-millisecond range.
|16:50 - 17:00||Closing|