Power optimization is the process of reducing the power consumption of a digital electronic design to its optimal level while preserving design functionality, safety, and security. The process uses electronic design automation tools and methodologies for optimal power levels. Finding the optimal power level requires fine-tuned analysis of the performance and area tradeoffs. Power optimization can be categorized as either static or dynamic. Dynamic power comprises switching and short-circuit power, while static power is leakage, or current that flows through the transistor when the device is inactive.

What Are the Challenges Associate with Power Optimization?

The increasing speed and complexity of today’s designs requires substantial increase in device power consumption. Adding to this challenge is the march to angstrom. This complexity means that manual power optimization is too slow and more than likely introduces errors.



Leakage power was the primary concern for design teams in the 90-to-20 nanometer range of planar process geometries because dynamic power was insignificant (10-15%) compared to its counterpart leakage power (85-95%). Once the industry shifted to FinFET processes at 16-to-14 nanometers, devices possessed improved control over leakage power. FinFETs are multigate devices built on a substrate where the gate is placed on two, three or four sides of the channel or wrapped around the channel, forming a double-gate, 3D structure. However, the multi-gate structure required higher power consumption each time a device switches, impacting dynamic power.



Smaller process geometries are forcing wires to get smaller and closer creating denser layouts. As this happens IR-drop becomes a factor. IR-drop, often referred to as voltage drop, refers to the decrease in voltage as current levels travel along any path with resistance. When the voltage supplied to a logic cell decreases and changes its delay, violations of setup and hold timing can result. Noise from the power supply nets from the on-chip power/ground grid can also be introduced.



Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore.


Power Management

Power intent needed for low power design techniques is captured through the IEEE Standard 1801 Unified Power Format (UPF). Designing the UPF file is a manual, tedious process and does not always scale from one abstraction level to another or from one tool to another in the SoC design flow. Designing and optimizing UPF needs a thorough understanding of the ever-evolving standard.


Power Analysis

Devices are designed to operate within a specific power envelope. Accurate power analysis to validate that power targets are met is challenging. Accurate power analysis happens too late in the traditional design flow to allow for design changes if power targets are missed. Designs are either taped out on time without meeting power specifications or schedule delays are incurred to ensure power targets are met. Both situations can incur significant costs and missed time-to-market windows.



Power-aware verification of advanced low power designs (both analog and digital) is a top concern for products at 32nm and below. Understanding verification coverage is a big hurdle to optimizing power for low power designs.

How Do You Achieve Optimal Power?

Design for low power does not occur in a single step. It involves a collection of techniques and methodologies aimed at reducing the overall dynamic and static power consumption. Design for optimal power is woven throughout the entire chip design process, and typically there are five main phases for a design and verification methodology that are used:

  1. Static Power Verification and Exploration
  2. Dynamic Power Verification and Analysis
  3. Software Driven Power Analysis
  4. Power Implementation
  5. Signoff

Synopsys offers software-driven low power exploration, analysis and optimization from architecture to signoff. The solution is built around industry-leading products for each stage of the design flow:

Platform Architect™ for architecture exploration and early performance power tradeoffs using pre-RTL architecture models and software workloads.

ZeBu® Empower for power emulation with the capacity and performance for profiling software workloads to identify key windows of interest for further analysis and exploration.

SpyGlass® Power for RTL power exploration with fast turnaround time during initial stages of RTL development.

PrimePower RTL with RTL Architect for RTL power exploration with high accuracy as the RTL matures.

Fusion Compiler™ for RTL to GDSII implementation with the best PPA (Power-Performance-Area) results. Fusion of PrimePower for signoff power and RedHawk Analysis Fusion for power integrity ensure fast convergence. IC Compiler II™ provides a production-proven place and route solution for physical implementation.

Synopsys TestMAX™ for power-optimized automatic test pattern generation (ATPG).

PrimePower for golden power signoff.

Verdi UPF Architect for automated UPF generation and optimization.

Verdi Power-Aware Debug provides a unified view of the design and its power intent, and an understanding and awareness of the impact of power intent on the design, in order to identify potential design-killing bugs early in the design flow.

PowerReplay for early power analysis with RTL simulation data.

Synopsys' advanced low power solution is comprised of VCS Native Low Power (NLP) and VC LP, an advanced low power static rules checker that offers comprehensive coverage for all advanced power management functions.

Synopsys' solutions enable SoC designers to achieve optimal energy efficiency by maximizing power-reduction opportunities at each stage of design flow while meeting PPA targets.

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