Design for low power does not occur in a single step. It involves a collection of techniques and methodologies aimed at reducing the overall dynamic and static power consumption. Design for optimal power is woven throughout the entire chip design process, and typically there are five main phases for a design and verification methodology that are used:
- Static Power Verification and Exploration
- Dynamic Power Verification and Analysis
- Software Driven Power Analysis
- Power Implementation
Synopsys offers software-driven low power exploration, analysis and optimization from architecture to signoff. The solution is built around industry-leading products for each stage of the design flow:
Platform Architect™ for architecture exploration and early performance power tradeoffs using pre-RTL architecture models and software workloads.
ZeBu® Empower for power emulation with the capacity and performance for profiling software workloads to identify key windows of interest for further analysis and exploration.
SpyGlass® Power for RTL power exploration with fast turnaround time during initial stages of RTL development.
PrimePower RTL with RTL Architect for RTL power exploration with high accuracy as the RTL matures.
Fusion Compiler™ for RTL to GDSII implementation with the best PPA (Power-Performance-Area) results. Fusion of PrimePower for signoff power and RedHawk Analysis Fusion for power integrity ensure fast convergence. IC Compiler II™ provides a production-proven place and route solution for physical implementation.
Synopsys TestMAX™ for power-optimized automatic test pattern generation (ATPG).
PrimePower for golden power signoff.
Verdi UPF Architect for automated UPF generation and optimization.
Verdi Power-Aware Debug provides a unified view of the design and its power intent, and an understanding and awareness of the impact of power intent on the design, in order to identify potential design-killing bugs early in the design flow.
PowerReplay for early power analysis with RTL simulation data.
Synopsys' advanced low power solution is comprised of VCS Native Low Power (NLP) and VC LP, an advanced low power static rules checker that offers comprehensive coverage for all advanced power management functions.
Synopsys' solutions enable SoC designers to achieve optimal energy efficiency by maximizing power-reduction opportunities at each stage of design flow while meeting PPA targets.