ASIP eUpdate, October 2018

ASIP Designer

Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.

This bi-annual newsletter provides you with easy access to ASIP related resources. This issue includes the following topics

Technology Feature: Debugging Throughout the Design Process

Efficient debugging support for the different phases of an ASIP lifecycle is essential for project success.

  • Design phase: requires efficient debugging solutions that enable analysis of both hardware and software at all stages of the development process.

  • Deployment phase: once integrated into a system-on-chip (SoC), embedded software developers expect an efficient software debugging solution.



One of the key methodologies supported by ASIP Designer is the “compiler-in-the-loop” approach. Thanks to the immediate availability of a compiler and an instruction set simulator, it is possible to analyze the performance of the architecture, and tune it as needed. This methodology calls for a debug solution that offers insight into both the software and the hardware description, as well as powerful profiling options. ASIP Designer’s native debug environment, called ChessDE, provides exactly this. Figure 1 shows a screen shot that highlights some of the options, including classical debug information like joint cross-debugging of source code and microcode, access to source code variables with their current mapping onto storages (i.e. registers or memory locations), and the option to modify storage values during the debug session. But in addition to this “classical” software debug information, ChessDE provides insight into the architecture, with the option to visualize how instructions proceed through the pipeline, and stepping through the statements of the processor model (nML/PDG code) in micro-steps, i.e. showing the behavior within a single clock cycle. ASIP Designer’s ability to generate a cycle-accurate instruction set simulator is of key importance for this step.

For multicore designs, a multicore version of ChessDE (named ChessMP) is available, which allows for fully synchronized debugging of multiple ASIPs.

Figure 1: Combined software and architecture debugging using ChessDE

Verdi Hardware/Software Co-Debug

Another key methodology supported by ASIP Designer is the “synthesis-in-the-loop” approach, as the RTL implementation of the ASIP can be immediately generated and synthesized for clock-speed, power, and area feedback. While the RTL code is automatically derived from the nML code, it is subject to functional verification, which is about simulating and eventually debugging the RTL code. So, it will be embedded into a testbench that runs the RTL – but in this case it also has to execute software. Efficient co-debugging of the hardware and software calls for a fully synchronized view on both. For this, ASIP Designer allows for a tight integration with Synopsys’ Verdi debug environment, providing a full HW/SW co-debug solution.  It combines the RTL view with a synchronized instruction-accurate view on C and assembly (see Figure 2).

Figure 2: Hardware/Software Debugging using Verdi

On-Chip Debugging

ASIP Designer allows for the easy setup of on-chip debugging (see Figure 3). The RTL generator supports the automatic generation of a processor debug controller (PDC) linked to a debug GUI. This link can be serial, based on the JTAG interface (with eight industry probes supported), or parallel, connecting with an APB™ debug bus using Arm® CoreSight™ infrastructure (with DSTREAM or Trace32 probe) or connecting with a UMRBus to debug on a HAPS® prototyping system. An API allows to add support for additional probes, as needed. The on-chip debugging solution is fully multi-ASIP aware.  ASIP Designer’s on-chip debug solution additionally supports the generation of short real-time traces (see below in the What’s New section).

Using ASIP Designer’s on-chip debugging technology, designers can continue to use the ChessDE and ChessMP graphical debuggers as they did in the earlier design phases, while running their embedded software on a hardware implementation of their ASIPs.

Figure 3: On-Chip Debugging

Software Debugging using Eclipse

On a multiprocessor SoC with processors from different vendors, sometimes an IDE based on the open-source Eclipse framework is used (Figure 4). To enable the software development and debugging of such heterogeneous multicore designs, ASIP Designer supports this setup, by providing plug-ins for integration into an Eclipse-based GUI. It is streamlined to the needs of an embedded software designer.

Figure 4: Eclipse-based debug environment

What’s New in ASIP Designer?

2018.09 Release Update

Since the April 2018 newsletter, ASIP Designer has again seen a number of enhancements and extensions. The following is an extract, sorted by categories (please refer to the official Release Notes for the comprehensive list).

Example Models

  • BLX: New model, a DLX variant illustrating how to design processors supporting branch prediction.

  • Verdi HW/SW debugging (a feature introduced in 2018.03) has been enabled for several example models.

  • The Tmicro model has been updated to illustrate the short real-time tracing concept. Such traces typically capture a few tens of program-counter states. The example illustrates the addition of a trace memory to the debug hardware, the introduction of commands to enable tracing mode and retrieve traced data, and the use of GUI plug-ins to control tracing and visualize traces in the ChessDE graphical debugger.

Processor Modeling

  • The PDG language that captures behavioral elements of the processor model now supports user-defined structure types to ease modeling of resources like cache lines and branch target buffers.

C/C++ Compiler

  • Previously, the compiler only applied software pipelining to the innermost loops of the software program.  This has now been extended to non-inner loops, which provides significant performance improvements when the inner loop has a small loop count.

  • The compiler now supports multi-register push-pop instructions, which provides the ability to save and restore multiple registers to the software stack with a single instruction.

  • The compiler’s LLVM-based front-end has been updated to LLVM version 7.0, with C++14, the default C++ version.

RTL Generation, Verification, and Synthesis Support

  • A new option in ASIP Designer’s RTL generator enables the automatic generation of error detection logic for registers and pipeline registers, motivated by safety requirements in the automotive industry. Error detection code bits are automatically added, which are constantly monitored, so unintended bit changes in registers are detected.

  • A new option enables the generation of UVM/SystemVerilog assertions monitoring for valid instructions, and instruction-set coverage.

Additional Resources

ASIP University Day 2018

On September 26th, Synopsys, in cooperation with RWTH Aachen University / Germany, organized the ASIP University Day 2018. Leading university teams presented results from their ongoing ASIP projects in domains such as 5G baseband and AI accelerators. Synopsys presented latest case studies and in-depth insight into the ASIP Designer technology. Teaching embedded processor design classes, and how to leverage ASIP Designer, was another subject of the day. To close the event, a reception allowed plenty of time for networking among participants.

The ASIP University Day 2018 was complemented by a free training/tutorial day on September 27th, with students diving deeper into the concepts of the nML language.

Check out the web page for more information.

Customer References

“To meet our customer-specific requirements, we are developing specialized processors and programmable accelerators that are fully optimized for performance, power, area, and code size, while offering the required flexibility,” said Thierry Brouste, Manager, Embedded Computing Solutions, STMicroelectronics. “Using ASIP Designer as our tool of choice gives us a significant competitive advantage, because it enables us to quickly develop complex and highly differentiated application-specific processors, while maximizing our design team’s efficiency through design automation and architecture exploration.”

RIKEN’s drug discovery molecular simulation platform team utilizes leading computational technologies using large-scale, high-speed supercomputers, specifically for molecular simulation technologies. These molecular simulators are used to identify drug behavior at the atomic level and help predict what structural formulas make for highly effective and selective drug candidates. Molecular dynamics (MD) simulations are computationally intensive and need petaflops of processing performance. RIKEN recognized that a general-purpose processor would not deliver the required performance, and so they decided to develop their own specialized custom processor using Synopsys’ ASIP Designer tool, and integrated 17 instances of the processor in a custom multicore chip.

White Papers   

In order to develop a proprietary processor that can stand the test of time, a highly functional SDK must be developed. The complexity, cost and duration of SDK development vary depending on the architecture of the processor and the skillset of the SDK developers. In this paper, we analyze the requirements for an SDK. We then introduce a tool-based methodology for SDK development based on Synopsys’ ASIP Designer tool suite.

Architectural exploration is at the heart of any ASIP design approach. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain.

For the SoC implementation of SDR baseband, most or all of the fixed-function logic blocks for physical layer processing are replaced by software running on processor(s). Heterogeneous multicore architectures are deemed better suited for SDR SoCs since they require less silicon area and consume less power.

Modern SoCs integrate dozens of complex system functions, each requiring its own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of fixed hardware accelerators no longer suffices. ASIPs can offer the best balance for each system function, and thus form the basis of new generations of multicore SoCs.

On-demand Webinar

The embedded vision market has embraced deep learning algorithms based on convolutional neural networks (CNNs). This market is now shifting to higher-volume and lower-cost devices. High image resolutions and frame rates are pushing computational needs into the tera-ops/s range. Continuous improvement in CNN graphs and deep learning algorithms lead designers to require flexible (yet still efficient) implementations.  Meanwhile, deep learning is also making its way into other application domains. For example, algorithms capturing dynamic temporal behavior in the form of recurrent neural networks (RNN) are being applied for sound processing and language translation systems. In such a dynamic environment, traditional SoC architectures with a microprocessor and hardwired accelerators no longer suffice. We will illustrate how application-specific processors (ASIPs) reconcile the needs for performance and flexibility, for both control (e.g. CNN/RNN activation) and data processing tasks (e.g. convolutions) in deep learning systems.


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