Synopsys and the RWTH Aachen University / Germany held the ASIP University Day 2018, an informal workshop to learn more about the exciting options ASIPs offer, and what it takes to develop them.
If you were there or if you you were not able to attend the event and would like furhter information, please contact us.
Wednesday, September 26, 2018
|8:30 - 9:00||Registration|
|9:00 - 9:45||Getting started … Application-Specific Processors (ASIPs) in System-on-Chip Design: Market and Technology Trends
Markus Willems, Synopsys
ASIPs have established themselves as an implementation option next to standard processors IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability. This talk will provide an introduction into Synopsys' ASIP Designer tool-suite, targeted markets, business models, and how Synopsys collaborates with university partners in this domain.
|9:45 - 10:30||ASIP Designer at ETH class: Extending the RISC-V ISA for Efficient Near-Sensor Data Analytic Algorithms
Pasquale Davide Schiavone, ETH Zuerich
Minimizing the power consumption is highly desirable to achieve multi-year lifetimes for battery-powered IoT endnodes. These endnodes are usually based on programmable microcontroller-class platforms to reduce the time-to-market and increase the products versatility. The PULP open-source project is a joint effort between ETH-Zurich and UniBologna which aims to develop an energy-efficient programmable platform based on the RISC-V ISA. Custom extensions to the ISA are possible for RISC-V cores thanks to the openness of the ISA and the availability of unoccupied regions in the opcode space. These extensions are key to increase the energy-efficiency in IoT applications when near-sensor data analysis is needed. To help students of our classes to understand how to extend a RISC-V core, we used ASIP Designer to explore processor customization using a fast and highly automated design flow.
|10:30 - 11:00||Coffee|
|11:00 - 11:45||Designing Application-Specific Processors for Deep Learning Acceleration
Gert Goossens, Synopsys
Deep learning is making its way into various application domains. The embedded vision market has embraced deep learning algorithms based on convolutional neural networks (CNN). Algorithms capturing dynamic temporal behavior in the form of recurrent neural networks (RNN) are being applied for sound processing and language translation systems. In such a dynamic environment, traditional SoC architectures with a microprocessor and hardwired accelerators no longer suffice. We will illustrate by example how ASIPs reconcile the needs for performance and flexibility.
|11.45 - 12:30||Design Perspectives of an ASIP for CNN Acceleration
Andreas Bytyn, RWTH Aachen
The rise of Convolutional Neural Networks (CNNs) has created the need for highly parallel processing architectures. While using systolic arrays yields the desired parallelism, most of the flexibility is lost. We present the design perspectives and challenges encountered while implementing a 4-slot VLIW processor with SIMD instructions that attempts to bridge the gap between performance and flexibility.
|12:30 - 13:30||Lunch|
|13:30 -14:15||Wireless Case Study: Minimum Mean Square Error (MMSE) Equalization in 5G New Radio
Werner Geurts, Synopsys
ASIPs see strong adoption in the field of 5G wireless communication. ASIPs enable product development before the 5G standard is finally frozen. At the same time, ASIPs provide the acceleration needed to achieve the high throughput and short latency requirements of 5G. As an example we will show the design of an ASIP for MMSE in 5G New Radio. We follow an “algorithm first” design process. Such process starts from a number of algorithms for which the architecture has to be optimized, and the definition of the throughput requirements. The presentation will provide an overview on main functional kernels of the MMSE algorithm, and the performance requirement in the context of the 5G standard. We will illustrate the architectural decisions that have to be taken, and how this process is being supported by ASIP Designer.
|14:15 - 15:00||ASIP Design for massive MIMO Baseband Processing
Steffen Malkowsky, Lund University
We present the current status of our 16-lane complex SIMD massive MIMO ASIP with planned features like pre- and post-processing slots for efficient mapping of massive MIMO signal processing algorithms as well as a specialized architecture to boost matrix calculations.
|15:00 - 15:30||Coffee|
|15:30 - 16:15||Custom Processor Design for Bayesian Networks
Nimish Shah, KU Leuven
A Bayesian network is a graphical model that represents probabilistic dependencies among a set of variables via a directed acyclicgraph (DAG). Its ability to model causal relations and uncertainty, handle missing data, and perform interpretable inference, makes it a powerful tool for machine learning. Often large Bayesian networks with hundreds of nodes are required to model real-life problems, and inference is made tractable by compiling these networks into circuits of sums and products, called arithmetic circuits. Yet, state-of-the-art is missing processors capable of efficiently computing such arithmetic circuits for energy-efficient embedded inference in Bayesian networks. We are developing a processor with a custom datapath that can exploit the typical data flow patterns in arithmetic circuits, using Synopsys ASIP tool. A preprocessing algorithm is developed to decompose an arithmetic circuit into processor-suitable subblocks, to assist the ASIP tool in the compilation.
|16:15 - 17:00||Technology InDepth: C/C++ Compilation Using ASIP Designer
Gert Goossens, Synopsys
ASIP Designer provides a C/C++ compiler even for highly specialized processor architectures. We will explain in detail the underlying concepts of this patented technology, and how to take advantage of it in your ASIP project for both architectural exploration and embedded software development.
|17:15 - 18:30||Happy Hour|