Cloud native EDA tools & pre-optimized hardware platforms
Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications
The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product. By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated.
Synopsys ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP. Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain.
This seminar introduces you to the ASIP Designer tool-suite. It features two case studies from popular application domains. The first case study by Lund University shows the design exploration for a RISC-V based VLIW processor for feature extraction in smart vision systems, using ASIP Designer. The second case study by Synopsys shows an ASIP for post-quantum cryptography. A RISC-V baseline architecture is gradually extended into an ASIP that is optimized for the Kyber encryption mechanism but accelerating also other cryptographic applications.
Falco Munsche, Technical Marketing Manager, Synopsys Germany
Kyber, the first standardized key encryption mechanism designed to withstand attacks with future powerful quantum computers, is computationally very demanding due to extensive use of hashing, for example. In this case study, an ASIP optimized for accelerating Kyber was developed, starting from an open-source implementation compiled and profiled on a RISC-V base model, gradually adding architectural specializations that go beyond simple RISC-V extension mechanisms. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step.