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About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design Automation (SIGDA) and IEEE's Council on Electronic Design Automation (CEDA).
Event Highlights
Introducing Synopsys Academic & Research Alliances (SARA)
Synopsys Academic & Research Alliances (SARA) was born through our commitment to growing relationships with universities beyond our University Software Program—please join us in celebrating students and professors at some of our sponsored events at DAC.
Young Fellows Program & Ecosystem Career Panel Lunch Sunday
Synopsys is excited to co-sponsor the Young Fellows Program, which provides an opportunity to connect and interact with students, and make a lasting impression on the next generation. As part of our commitment to empower future engineering talent, SARA will hold an ecosystem career panel on Sunday, July 10 from 12-2:15pm. to share more about different roles at Synopsys and our customers. If you are a Young Fellow at DAC, please complete your registration to attend.
Register HereProfessor Breakfast
If you are a professor attending the event, we want to meet you to learn more about your work. We will be hosting a speed networking event where you can learn more about how you can accelerate and improve your teaching, curriculum development, and research. We cordially invite you to the Professor Breakfast, Wednesday, July 13 at 7:30 a.m.
Register HerePh.D. Forum at DAC
The Ph.D. Forum at DAC is a poster session hosted by ACM SIGDA for Ph.D. students to present and discuss their dissertation research with the EDA community. Please save the date and time and join us as we recognize their work on Tuesday, July 12 at 7 p.m.
Learn MoreHACK@DAC
Synopsys is proud to sponsor HACK@DAC for a second year—a competition focusing on penetration testing of hardware and firmware. Participants will compete to identify security vulnerabilities, implement the related exploit, propose a mitigation technique or a patch, and report them. Finalists will compete in a live capture-the-flag competition during DAC, and winners will be announced on Tuesday, July 12 at 3:30 p.m. during DAC.
Learn MoreAlso Don't Miss!
While you enjoy your coffee at booth #1320, why not join us to engage with our Synopsys innovators for our unique Synopsys Speaks! initiative? Learn how Synopsys employees are leading the way in solving industry challenges through passion, innovation, and collaboration.
Monday, July 11
- 1:45 p.m.: Pawini Mahajan, Product Marketing Manager, TestMAX
- 2:45 p.m.: Weikai Sun, VP, Engineering
- 3:45 p.m.: Renu Mehra, VP, Engineering
Tuesday, July 12
- 1:45 p.m.: Ron Duncan, Senior Manager, Applications Engineering
- 2:45 p.m.: Deepashree Sengupta, R&D Engineer, Staff
- 3:45 p.m.: Radhika Shankar, Group Director, Applications Engineering
Wednesday, July 13
- 11:45 a.m.: Sashi Obilisetty, Group Director, R&D
PrimeTime SIG
Join us at Synopsys PrimeTime SIG, taking place during DAC on the evening of Monday, July 11. A great lineup of customers and partners will share their experiences and results using Synopsys signoff tools and methodologies to achieve their design goals with high accuracy while accelerating design closure. Please visit the event page here to learn more and register.
Designing 3D-ICs in a 2D World
Start your Tuesday morning at DAC by attending our panel discussion on 3D-IC design while enjoying a full breakfast before the exhibit floor opens. Synopsys and Ansys are co-sponsoring a panel of leading customers and industry executives who will discuss their experiences with adopting 2.5D/3D-IC manufacturing technology for standard semiconductor products and bespoke silicon solutions. Space is limited so please register today to secure your spot.
Sessions Spotlight
Hear from Synopsys speakers at a variety of venues throughout the conference.
Synopsys & IFS - Enabling RISC-V Design Solutions
Speaker: Kiran Vittal
Time: 11:20 a.m. - 11:40 a.m. PDT
Location: Intel Foundry Services Booth #2325
Transforming EDA Time-to-Market with Synopsys Cloud
Speaker: Vikram Bhatia
Time: 11:30 a.m. - 12:15 p.m. PDT
Location: Design-on-Cloud Theater, Booth #1258
Bring Your Semiconductor Designs to Market Faster Using Synopsys Cloud on Microsoft Azure
Speaker: Vikram Bhatia
Time: 3:10 p.m. - 3:55 p.m. PDT
Location: Microsoft Booth #1252
Memory Read Yield Estimation Using High Sigma Monte Carlo
Speaker: Rakesh Shenoy
Time: 3:30 p.m. - 3:45 p.m. PDT
Location: Room 2012
Open Source Hardware to Enable Faster TTR
Organizer: Sashi Obilisetty
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: Room 2010
The Hardware/Software Nexus in Chip Design
Organizer: Sabya Das
Speaker: Olivier Coudert
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: Room 2008
Verifying I/O Designs Using Symbolic Simulation to Increase Design and Model Robustness
Speakers: Rakesh Shenoy, Moninder Singh
Time: 4:00 p.m. - 4:15 p.m. PDT
Location: Room 2012
Static Timing and Power Analysis with Process Space Exploration
Speakers: Asheesh Baghel, Ruijing Shen, Mayur Bubna, Li Ding
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Automated Timing-aware Dynamic Voltage Drop ECO
Speakers: Len Hsu, KH Kim
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Speakers: Amit Goldie, Himanshu Kathuria, Sampath Amarasinghe
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Cell EM Aware Design Optimization
Speakers: Jinmo Jung, Vivek Panure
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Design Timing Effects of Layer-to-Layer Interconnect Skew
Speakers: Ayhan Mutlu, Duc Huynh, Jian-Feng Chen, Li Ding
Time: 5:10 p.m. - 5:20 p.m. PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
Delivering Technological and Productivity Innovations to Drive Design in SysMoore Era
Speaker: Shekhar Kapoor
Time: 5:30 p.m. - 6:00 p.m. PDT
Location: Samsung Booth #2355
Machine Learning for Synthesis and Synthesis for Machine Learning
Session Chair: Sripada Subramanyam
Time: 10:30 a.m. - 12:00 p.m. PDT
Location: Room 3004
Creating Robust EDA and IP Ecosystems to Strengthen the Global Semiconductor Supply Chain
Speaker: Bari Biswas
Time: 10:30 a.m. - 12:00 p.m. PDT
Location: Room 2012
VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Speakers: Varun Gunnala, Dong-Hyun Lee
Time: 11:00 a.m. - 11:15 a.m. PDT
Location: Room 2008
Bring Your Semiconductor Designs to Market Faster Using Synopsys Cloud on Microsoft Azure
Speaker: Sridhar Panchapakesan
Time: 11:10 a.m. - 11:55 a.m. PDT
Location: Microsoft Booth #1252
Synopsys Fusion Design Platform and IFS Enabling Next-Generation SoCs
Speaker: Arvind Narayanan
Time: 1:00 p.m. - 1:20 p.m. PDT
Location: Intel Foundry Services Booth #2325
Unleashing Full Analog Design and Simulation Environment on Optimized Cloud
Speaker: Teng-Kiat Lee
Time: 1:30 p.m. - 2:15 p.m. PDT
Location: Design-on-Cloud Theater, Booth #1258
A Scalable Symbolic Simulation Tool for Low Power Embedded Systems
Speaker: Hari Cherupalli
Time: 1:53 p.m. - 2:15 p.m. PDT
Location: Room 3004
Women in Engineering: Transforming the Innovation Paradigm
Speaker: Radhika Shankar
Time: 2:00 p.m. - 2:45 p.m. PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
New Directions in Silicon Solutions
Organizer: Sashi Obilisetty
Speaker: Yervant Zorian
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: Room 2008
Improving LUT-Based Optimization for ASIC
Speakers: Luca Amaru, Patrick Vuillod, Jiong Luo
Time: 3:50 p.m. - 4:10 p.m. PDT
Location: Room 3007
Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Speaker: Khader Abdel-Hafez, YongJoon Kim
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Speaker: Dongli Song
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Speaker: Min Pan, Tong Liu
Time: 6:00 p.m. - 7:00 p.m. PDT
Location: Level 2 Lobby
How Fast Can You Go? It is a Mad, Mad, Mad, Mad Placement World!
Session Chair: Siddhartha Nath
Time: 10:30 a.m. - 12:00 p.m. PDT
Location: Room 3007
It’s Getting Cloudy Out There
Speaker: Sandeep Mehndiratta
Time: 1:00 p.m. - 1:45 p.m. PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
Cryogenic Computing, Super Cool or Not?
Speaker: Jamil Kawa
Time: 1:30 p.m. - 3:00 p.m. PDT
Location: Room 3001
Future Unleashed: Beyond-CMOS Meets the Real World
Session Chair: Luca Amaru
Time: 3:30 p.m. - 5:30 p.m. PDT
Location: Room 3002
Multi-Die Systems and HPC Requirements
Session Chair: John Koeter
Time: 4:30 p.m. - 5:00 p.m. PDT
Location: Samsung Booth #2355
FPopt: ML-Based Chip Floorplan Optimization
Speakers: Joe R Walston, Varun Gunnala, Dong-Hyun Lee
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Automating Analog Layout - Has the Time Finally Come?
Speaker: Weikai Sun
Time: 1:30 p.m. - 3:00 p.m. PDT
Location: Room 3001
Keep Moving up and Looking Sideways with Verification Boosters!
Session Chair: Maheshwar Chandrasekar
Time: 3:30 p.m. - 5:30 p.m. PDT
Location: Room 3000
So You Want a Better Design? Go with Faster Timing and Lower Power Please!
Session Chair: Karthi Duraisamy