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About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design Automation (SIGDA) and IEEE's Council on Electronic Design Automation (CEDA).
Event Highlights
Introducing Synopsys Academic & Research Alliances (SARA)
Synopsys Academic & Research Alliances (SARA) was born through our commitment to growing relationships with universities beyond our University Software Program—please join us in celebrating students and professors at some of our sponsored events at DAC.
Young Fellows Program & Ecosystem Career Panel Lunch Sunday
Synopsys is excited to co-sponsor the Young Fellows Program, which provides an opportunity to connect and interact with students, and make a lasting impression on the next generation. As part of our commitment to empower future engineering talent, SARA will hold an ecosystem career panel on Sunday, July 10 from 12-2:15pm. to share more about different roles at Synopsys and our customers. If you are a Young Fellow at DAC, please complete your registration to attend.
Register HereProfessor Breakfast
If you are a professor attending the event, we want to meet you to learn more about your work. We will be hosting a speed networking event where you can learn more about how you can accelerate and improve your teaching, curriculum development, and research. We cordially invite you to the Professor Breakfast, Wednesday, July 13 at 7:30 a.m.
Register HerePh.D. Forum at DAC
The Ph.D. Forum at DAC is a poster session hosted by ACM SIGDA for Ph.D. students to present and discuss their dissertation research with the EDA community. Please save the date and time and join us as we recognize their work on Tuesday, July 12 at 7 p.m.
Learn MoreHACK@DAC
Synopsys is proud to sponsor HACK@DAC for a second year—a competition focusing on penetration testing of hardware and firmware. Participants will compete to identify security vulnerabilities, implement the related exploit, propose a mitigation technique or a patch, and report them. Finalists will compete in a live capture-the-flag competition during DAC, and winners will be announced on Tuesday, July 12 at 3:30 p.m. during DAC.
Learn MoreAlso Don't MIss!
Synopsys Lounge
Grab a cup of coffee on us at the Synopsys Lounge (Booth #1320).
Meet our experts or just relax and recharge using our convenient charging stations. More details to come soon!
PrimeTime SIG
Join us at Synopsys PrimeTime SIG, taking place during DAC on the evening of Monday, July 11. A great lineup of customers and partners will share their experiences and results using Synopsys signoff tools and methodologies to achieve their design goals with high accuracy while accelerating design closure. Please visit the event page here to learn more and register.
Designing 3D-ICs in a 2D World
Start your Tuesday morning at DAC by attending our panel discussion on 3D-IC design while enjoying a full breakfast before the exhibit floor opens. Synopsys and Ansys are co-sponsoring a panel of leading customers and industry executives who will discuss their experiences with adopting 2.5D/3D-IC manufacturing technology for standard semiconductor products and bespoke silicon solutions. Space is limited so please register here today to secure your spot.
Sessions Spotlight
Hear from Synopsys speakers at a variety of venues throughout the conference.
Transforming EDA Time-to-Market with Synopsys Cloud
Speaker: Vikram Bhatia
Topic: Design-on-Cloud
Time: 11:30 a.m. - 12:15 p.m. PDT
Location: Design-on-Cloud Theater, Booth #1258
Memory Read Yield Estimation Using High Sigma Monte Carlo
Speaker: Rakesh Shenoy
Topic: Engineering Tracks, IP
Time: 3:30 p.m. - 3:45 p.m. PDT
Location: Room 2012, Level 2
Open Source Hardware to enable faster TTR
Speaker: Sashi Obilisetty (Organizer)
Topic: Engineering Tracks, IP
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: Room 2010, Level 2
The Hardware/Software Nexus in Chip Design
Speaker: Sabya Das (Organizer), Olivier Coudert
Topic: Back-End Design, Engineering Tracks
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: Room 2008, Level 2
Verifying I/O Designs Using Symbolic Simulation to Increase Design and Model Robustness
Speaker: Rakesh Shenoy, Moninder Singh
Topic: Engineering Tracks, IP
Time: 4:00 p.m. - 4:15 p.m. PDT
Location: Room 2012, Level 2
Static Timing and Power Analysis with Process Space Exploration
Speaker: Asheesh Baghel, Ruijing Shen, Mayur Bubna, Li Ding
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Automated Timing-aware Dynamic Voltage Drop ECO
Speaker: Len Hsu, KH Kim
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Speaker: Amit Goldie, Ankush Bagotra, Himanshu Kathuria, Sampath Amarasinghe
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Cell EM aware Design Optimization
Speaker: Jinmo Jung, Vivek Panure
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Design Timing Effects of Layer-to-Layer Interconnect Skew
Speaker: Ayhan Mutlu, Duc Huynh, Jian-Feng Chen, Li-Chung Hsu, Li Ding
Topic: DAC Pavilion Gladiator Arena Poster Battle, Engineering Track Poster, Engineering Tracks
Time: 5:10 p.m. - 5:20 p.m. PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
Machine Learning for Synthesis and Synthesis for Machine Learning
Speakers: Sripada Subramanyam (Session Chair)
Topic: Research Manuscript
Time: 10:30 a.m. - 12:00 p.m. PDT
Location: Room 3004, Level 3
Creating Robust EDA and IP Ecosystems to Strengthen the Global Semiconductor Supply Chain
Speakers: Bari Biswas
Topic: Executive Panel, Engineering Tracks, IP
Time: 10:30 a.m. - 12:00 p.m. PDT
Location: Room 2012, Level 2
VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Speaker: Varun Gunnala, Donghyun Lee
Topic: Back-End Design, Engineering Tracks
Time: 11:00 a.m. - 11:15 a.m. PDT
Location: Room 2008, Level 2
A Scalable Symbolic Simulation Tool for Low Power Embedded Systems
Speaker: Hari Cherupalli
Topic: Research Manuscript
Time: 1:53 p.m. - 2:15 p.m. PDT
Location: Room 3004, Level 3
Women in Engineering: Transforming the Innovation Paradigm
Speaker: Radhika Shankar
Topic: DAC Pavilion Panel
Time: 2:00 p.m. - 2:45 p.m. PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
New Directions in Silicon Solutions
Speaker: Sashi Obilisetty (Organizer), Yervant Zorian
Topic: Back-End Design, Engineering Tracks
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: Room 2008, Level 2
Improving LUT-Based Optimization for ASIC
Speaker: Luca Amaru, Vinicius Possani, Patrick Vuillod, Jiong Luo
Topic: Research Manuscript
Time: 3:50 p.m. - 4:10 p.m. PDT
Location: Room 3007, Level 3
Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Speaker: Khader Abdel-Hafez, YongJoon Kim
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Speaker: Dongli Song
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Speaker: Min Pan, Tong Liu
Topic: Networking Reception, Work-in-Progress Poster
Time: 6:00 p.m. - 7:00 p.m. PDT
Location: Level 2 Lobby
How Fast can you go? It is a mad, mad, mad, mad placement world!
Speaker: Siddhartha Nath (Session Chair)
Topic: Research Manuscript
Time: 10:30 a.m. - 12:00 p.m. PDT
Location: Room 3007, Level 3
It’s Getting Cloudy Out There
Speaker: Sandeep Mehndiratta
Topic: SKYTalk
Time: 1:00 p.m. - 1:45 p.m. PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
Cryogenic Computing, Super Cool or Not?
Speaker: Jamil Kawa
Topic: Research Panel
Time: 1:30 p.m. - 3:00 p.m. PDT
Location: Room 3001, Level 3
Future Unleashed: Beyond-CMOS Meets the Real World
Speaker: Luca Amaru (Session Chair)
Topic: Research Manuscript
Time: 3:30 p.m. - 5:30 p.m. PDT
Location: Room 3002, Level 3
FPopt: ML-Based Chip Floorplan Optimization
Speaker: Joe R Walston, Varun Gunnala, Donghyun Lee
Topic: Engineering Track Poster, Engineering Tracks
Time: 5:00 p.m. - 6:00 p.m. PDT
Location: Level 2 Exhibit Hall
Automating Analog Layout - Has the time finally come?
Speaker: Weikai Sun
Topic: Research Panel
Time: 1:30 p.m. - 3:00 p.m. PDT
Location: Room 3001, Level 3
Keep moving up and looking sideways with verification boosters!
Speaker: Maheshwar Chandrasekar (Session Chair)
Topic: Research Manuscript
Time: 3:30 p.m. - 5:30 p.m. PDT
Location: Room 3000, Level 3
So You Want a Better Design? Go with Faster Timing and Lower Power Please!
Speaker: Karthi Duraisamy (Session Chair)
Topic: Research Manuscript