International Test Conference

October 10 - 15, 2021
A Virtual Experience

The Synopsys TestMAX™ family offers innovative test and diagnosis for digital logic and memory, enabling a unified flow that is securely connected to Synopsys’ Fusion Design Platform and Silicon Lifecyle Management Platform for silicon analytics, meeting both design and test goals concurrently.

 

Synopsys Keynote

Shankar Krishnamoorthy

General Manager Digital Design Group & Corporate Staff

Addressing Design Challenges in the Era of SysMoore: From Architecture to Silicon Lifecycle Management

Thursday, October 14, 2021

8:00 a.m. - 8:30 a.m.  PDT

Amount of compute power required in today’s SoCs, especially in AI applications, is outpacing Moore’s Law by a wide margin. Orders of magnitude compute are needed to keep pace with this new era of scaling and system complexity, otherwise known as the SysMoore era. In this presentation we examine the challenges driving the next wave of innovative design solutions. Starting with architecture exploration to silicon-lifecycle management, these solutions  will help engineers create designs that keep pace with the compute power and silicon health needs for today and tomorrow.​

 

Panel Sessions

Tuesday, October 12
2:00 p.m. – 3:00 p.m. PDT
Panel 2: IEEE 1149.10: Is it The Best High-Speed I/O Test Method?
Organizers: Ramsay Allen/Robert Ruiz, Synopsys
Moderator: Anne Meixner
Panelists:
Claudia Bertani, ST Microelectronics
Klaus-Dieter Hilliges, Advantest-Europe
Steve Pateras, Synopsys
Suketu Bhatt, Intel

 

Thursday, October 14
9:30-10:30 AM PDT

SESSION 5D Accellera FuSa WG: Automation, Interoperability and Traceability in Functional Safety Standardization
Moderators: Alessandra Nardi, Cadence; Nir Maor, Qualcomm
Discussants:
Prasanth Viswanathan Pillai, Texas Instruments
Kaushik De, Synopsys
Bala Chavali, AMD

 

Thursday, October 14
2:00 p.m. – 3:00 p.m. PDT
Panel 4: Challenges of 3rd Party IPs to Achieve Automotive Zero-Defect Quality and Functional Safety
Organizer and Moderator: Chen He, NXP
Panelists:
Davide Appello, ST Microelectronics
Wim Dobbelaere, ON Semiconductor
Fei Su, Intel
Daniel Tille, Infineon
Jody Defazio, Synopsys
John Xu, Xscend Technology

 

Synopsys Tutorials and Session Papers

 

 

Monday, October 11
8:00 –11:00 a.m.​ PDT
Silicon Lifecycle Management for Emerging Memories​
Synopsys Presenter: Yervant Zorian

 

Monday, October 11​
12:00 – 3:00 p.m.​ PDT
Automotive Functional Safety, Reliability and Test Solutions
Synopsys Presenter: Yervant Zorian

 

Wednesday, October 13
2:00 – 3:00 p.m.​ PDT
Current Developments in Test Standards​
Synopsys Presenter: Mike Ricchetti

 

Synopsys Virtual Booth

Exhibit Hours:

Tuesday, October 12 - Thursday, October 14
9:00 a.m. – 9:30 a.m
10:30 a.m. – 11:00 a.m.
1:00 p.m. – 2:00 p.m.
All times are Pacific Daylight Savings Time

Visit us in our virtual booth and Meet with Us on the following topics:

  • TestMAX Overview
  • TestMAX Update
  • Power-Aware Test
  • TestMAX SMS
  • TestMAX Diagnosis
  • TestMAX FuSa
  • PrimeSim Custom Fault
  • TestMAX Roadmap
  • Silicon Lifecycle Management Overview
  • High-Speed Access and Test
  • Z01X Functional Fault Simulation

Session Posters

Wednesday, October 13 I 2:00 p.m. - 3:30 p.m. PDT

Power-Aware ATPG Using Sign-Off Models
K. Abdel-Hafez, A. Cron, Synopsys
W. Hsueh, S. Lai, MediaTek

A Novel Fault Grading Technique to Establish RTL-ATPG TopOff Coverage
P. Mahajan, H. Eriksson, F. Shukla, Synopsys
K. Adebo, E. Brazil, S. Pillai, Intel

In-Field Embedded Sensing & PVT Monitoring for Increased Device Power and Performance Optimization
R. Allen, Synopsys

Unified Test Flow for DFT Power, Performance & Area Optimization
S. Duggirala, R. Singhal, Synopsys

A Multi-Threaded Single-Pass Diagnosis of Scan Chain Failures
E. Gizdarski, Y. Kanzawa, Synopsys

 

Co-located Workshops

6th Automotive Reliability, Test and Safety Workshop

 

Thursday October 14
3:30 p.m. – 5:00 p.m. PDT

Opening of the sixth Automotive Reliability, Test and Safety Workshop
General Chairs: Yervant Zorian, Synopsys, Davide Appello, STM, Nir Maor, Qualcomm


Friday, October 15
9:00 a.m. – 9:50 a.m. PDT

Technical Session 1 – In-field Reliability and Hardware Security of Automotive Components and Systems:
Mitigating Soft Errors’ Impact On System Reliability
Ghani Kanawati, Magnus Bruce, Teresa McLaurin, Jim Dodrill, ARM 
Jamileh Davoudi, Brian Davenport, Synopsys 


Friday, October 15 
11:10 a.m. – 12:25 p.m. PDT 

Special session on Functional Safety
In-System Automotive Test Solution for External Memories

Yehonatan Abotbol, Grigor Tshagharyan, Arun Kumar, Gurgen Harutyunyan
Intel Mobileye, Synopsys

SoC Safety Management and Diagnostics with the ARC Safety Island and SHS/SMS
Fergus Casey, Srini Krishnaswami, Karen Darbinyan,  Synopsys

 

IEEE International Workshop on Silicon Lifecycle Management

Thursday, October 15
3:30 p.m. – 5:00 p.m. PDT

Opening of the 1st IEEE International Workshop on Silicon Lifecycle Management Workshop

General Chair: Yervant Zorian, Synopsys 
General Vice Chair: Krishnendu Chakrabarty, Duke U


Friday, October 15
8:45 a.m. – 9:40 a.m. PDT

The Critical Role of In-Silicon Visibility, Measurement, and Intelligent Analysis from Design to In-Field
Ramsay Allen


Friday, October 15
10:45 a.m. – 11:50 a.m. PDT

Leveraging SLM Monitors for IP characterization and Bring Up
Gurgen Harutyunyan

 

Friday, October 15
1:40 p.m. - 3:00 p.m. PDT

Panel: The Silicon Lifecycle Management Ecosystem at Large

Moderator: Robert Jin, NXP Semiconductors 
Panelists: 
Serge Leef, DARPA
John Oakley, Semiconductor Research Corporation
Anis Jarrar, NXP Semiconductors 
Yervant Zorian, Synopsys
Krishnendu Chakrabarty, Duke University
Mark Tehranipoor, University of Florida