Join the design and test community at the Synopsys Test & SLM Forum to hear how industry leaders are tackling the growing complexity of semiconductor design, test, and lifecycle management. Discover how AI-driven test, advanced design-for-test, in-chip monitoring, diagnosis, and silicon analytics are being used to improve productivity, accelerate yield learning, and strengthen silicon quality and reliability. Connect with peers and Synopsys experts over cocktails, dinner, and networking.
Monday, October 12, 2026 | 6:00 PM – 9:30 PM CT
Discover how Synopsys TestMAX™ and Silicon Lifecycle Management (SLM) solutions help engineering teams address the growing challenges of advanced packaging, AI systems, and increasingly complex semiconductor designs. From test and diagnosis to in-chip monitoring and silicon analytics, Synopsys delivers the technologies needed to improve quality, reliability, and operational efficiency throughout the silicon lifecycle.
Exhibit Hours
Live Demonstrations
See the latest advances in AI-driven test, silicon analytics, in-chip monitoring, and pre-silicon validation through interactive demonstrations at booth #302.
Let's Meet
Whether you want a quick chat to catch up or want to go deep on details, please reach out to us to schedule an on-site meeting.
For the full program please view here.
| Date | Time | Type | Session | Speaker | Company | Location |
| 12-Oct-26 | 8:30 am - 12:00 pm | Tutorial | 3DIC Advanced Packaging, Test & SLM | Sandeep Goel Yervant Zorian | TSMC Synopsys | Travis CD |
| 12-Oct-26 | 1:00 - 4:30 pm | Tutorial | UCIe based Multi-Chiplets Design & Test | Debendra Das Sharma Yervant Zorian | Intel Synopsys | Travis CD |
| 12-Oct-26 | 1:00 - 4:30 pm | Tutorial | In-Field System Test & Debug | Amit Pandey Karthik Natarjan Sankaran Menon | Amazon Synopsys Ercisson | Crockett CD |
| 13-Oct-26 | 5:15 - 5:30 pm | Short Paper | Speeding up DFT Recommendation Systems with limited-compute resources | Baleegh Ahmad Prakyath Madadi Zhiwei Liao Theo Toulas Peter Wohl | Synopsys | Travis AB |
| 14-Oct-26 | 12:00 - 2:00 pm | Poster Session | Breaking the SoC Test Bottleneck: Faster, Protocol-Free High-Speed Test I/O | Arpit Vijayvergia Surendra Kumar Nitin Bansal Mohit Garg Kunal Lakhani | Synopsys | Texas Ballroom DEF |
| 15-Oct-26 | 11:30 - 12:00 pm | Session | Accelerated DFT Optimization Using Compression-aware ATPG Emulation | Zhiwei Liao Jose Angel Duarte Mona Marmash Sruthi Nanduru Khader Abdel-Hafez Theo Toulas | Synopsys | Crockett AB |
| 16-Oct-26 | 8:00 - 9:00 am | Workshop | AI Methodology + 2 Application Talks | TBC | Synopsys | Republic ABC |