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Synopsys at Chiplet Summit
The semiconductor industry is accelerating innovation with multi-die design, driving new breakthroughs in IP and AI-powered EDA flows. Synopsys leads the way, helping companies deliver advanced multi-die designs to market with speed and precision. Join us at Chiplet Summit 2026 for our keynote and technical sessions, and visit our booth to connect with experts and see how Synopsys can drive your next innovation forward.
Synopsys Sessions
| Session Title/Presenter | Date/Time | Location |
| Pre-Con C: Advanced Packaging Methods AI-Driven Package Design from Architecture to Signoff Shawn Nikoukary, Director, Product Management |
Tuesday, February 17 8:30 AM–12:00 PM |
GAB K |
| Superpanel: Best Way to Make Chiplets Work (sponsored by Keysight Technologies) Big Question Frank Schirrmeister, Executive Director, System Solutions |
Tuesday, February 17 1:00 PM–2:00 PM |
GAB J |
| Keynote 1: Synopsys Designing the Future Today: AI-Driven Multi-Die Design Abhijeet Chakraborty, VP, Engineering |
Wednesday, February 18 10:10 AM–10:40 AM |
GAB J/K |
| A-101: Security Multiphysics Modeling for Early Vulnerability Mitigation Lang Lin, Director, Product Management |
Wednesday, February 18 2:30 PM–3:30 PM |
GAMR 1 |
| B-101: Die-to-Die Interfaces - 1: Advanced Technology Multi-Protocol Integration and Verification Using UCIe Anunay Bajaj, Solutions Architect |
Wednesday, February 18 2:30 PM–3:30 PM |
GAMR 2 |
| A-102: Design - 1 Leveraging Full-Wave Finite Element Methods for Chiplet Packaging Tunir Dey, Director, Product Management |
Wednesday, February 18 3:45 PM–4:45 PM |
GAMR 1 |
| A-102: Design - 1 AI Innovation in EDA for Chiplet Designs Anand Thiruvengadam, Director, Product Management |
Wednesday, February 18 3:45 PM–4:45 PM |
GAMR 1 |
| B-102: Die-to-Die Interfaces - 2: Advanced Packaging Comprehensive Overview of UCIE-A IP with CoWoS Tape Out Esha Dubey, Director, Product Management |
Wednesday, February 18 3:45 PM–4:45 PM |
GAMR 2 |
| E-102: Designing the Future: Integrating Heterogeneous Chiplets at Scale (Panel) Shekhar Kapoor, Executive Director, Product Line Management |
Wednesday, February 18 3:45 PM–4:45 PM |
Room 203 |
| G-102: Forum on Hardware-in-the-Loop for Chiplets (sponsored by Synopsys) Forum on Enabling the Compute and AI Chiplet Ecosystem with Hardware-Assisted Development Frank Schirrmeister, Executive Director, System Solutions; Ritesh Goel, Executive Director, Strategic Systems |
Wednesday, February 18 3:45 PM–4:45 PM |
Room 209 |
| H-102: What Developers Must Know about Automotive Chiplets (Panel) Hezi Saar, Executive Director, Mobile Automotive Consumer Product Management |
Wednesday, February 18 3:45 PM–4:45 PM |
Room 210 |
| D-103: Annual Update on Chiplet Design Chiplets for AI Data Centers: Challenges, Shift Left Strategies, 3D, Co-Packaged Optics Rob Kruger, Director, Product Management |
Wednesday, February 18 5:00 PM–6:00 PM |
GAB J |
| A-201: Design - 4 HBM Modeling for Advanced Chiplet Integration Takeo Tomine, Director, Product Management |
Thursday, February 19 9:00 AM–10:00 AM |
GAMR 1 |
| B-201: Die-to-Die Interfaces - 4: Advanced Applications Designing Die-to-Die Links for 64Gbps and Beyond Aparna Tarde, Sr. Product Manager, Product Management |
Thursday, February 19 9:00 AM–10:00 AM |
GAMR 2 |
| A-202: Testing DFT Architectural Challenges for MultiDie Stacking Applications Adam Cron, Distinguished Architect; Manish Arora, Director, Solutions Engineering |
Thursday, February 19 3:00 PM–4:20 PM |
GAMR 1 |
| B-203: Chiplets in 2031 and How We Got There (Panel) Norman Chang, Fellow/Chief Technologist |
Thursday, February 19 4:30 PM–5:50 PM |
GAMR 3 |
Exhibits
Wednesday, February 18 | 12:30 – 8:00 PM
Thursday, February 19 | 12:00 – 3:00 PM
Visit the Synopsys booth #400 to see the latest multi-die solutions from silicon to systems.
Synopsys Demos:
- 3D Construction & Auto Routing
- 2.5D/3D Interposer Design & Optimization
- Power-Efficient, High-Bandwidth Die-to-Die Connectivity
- Next-Gen IP for Scale Up & Out