ASIP eUpdate, April 2021

ASIP Designer

Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.

This bi-annual newsletter provides you with easy access to ASIP-related resources.

Technology Feature: Integration of ASIP Design into SoC Design and Verification Flows

Designing an ASIP is all about designing a processor optimized for power, performance and area (PPA) with an instruction-set tailored for a domain or set of applications. An efficient ASIP design methodology, therefore, has to support a tight integration with synthesis and verification flows. As a part of Synopsys’ broad portfolio of solutions, ASIP Designer strongly leverages access to Synopsys design and verification methodologies, tools, and expertise.

Examples include hardware implementation analysis and PPA refinement with RTL Architect, the generation of optimized synthesis scripts for Fusion Compiler and Design Compiler® NXT, hardware/software debug support with Verdi®, fast emulation with ZeBu® Server, and a tight link with prototyping solutions, including Virtualizer™ virtual prototyping and HAPS® FPGA-based prototyping.

ASIP Designer is tightly integrated into hardware design and verification flows.

Figure 1: ASIP Designer is tightly integrated into hardware design and verification flows

The generation of fully synthesizable RTL from the nML model is an integral part of ASIP Designer. nML enables both the instruction set as well as the microarchitecture of your design to be defined, which has an obvious impact on the generated RTL. ASIP Designer’s RTL generation can be steered towards certain optimization goals, with many options to choose from. The 2020.03 release introduced a new interactive table that simplifies the selection of these options, providing filtering and search functionalities and direct access to the option’s description.   

With the availability of synthesizable RTL, PPA performance is no longer an abstract term, but it is possible to measure, applying the real RTL-to-GDSII tool flow. To accelerate this step, ASIP Designer automatically generates the scripts for Synopsys Design Compiler NXT and Fusion Compiler according to the Synopsys Reference Implementation Flow.

Given ASIP architectures can be fairly large (and ASIP Designer can handle extremely complex designs), full synthesis and routing can take its time. When still in the architecture exploration phase, i.e. exploring the PPA impact of different architectural alternatives, it is often desired to shorten that cycle not using the final results, but very close estimates. That is why with 2021.03, ASIP Designer also integrates with the newly released RTL Architect tool from Synopsys. RTL Architect predicts the power, performance, area and congestion impact of RTL changes. Its estimates get close to the final implementation, as it leverages the algorithms of the Fusion Compiler platform, while taking only a portion of the time of full synthesis and routing. RTL Architect is tailored to analyze and compare alternative implementations, so it becomes an excellent solution during this phase of the design process.

RTL-Architect, analyzing the impact of three different RTL versions, resulting from selecting different Generation Options in ASIP Designer

Figure 2: RTL Architect, analyzing the impact of three different RTL versions, resulting from selecting different generation options in ASIP Designer

We refer to this methodology as Synthesis-in-the-Loop: It is about generating RTL as early as possible in the design process, to make sure that PPA implications and routing congestions are identified early, when they are still cheap to fix. This might identify the need to modify the depth of the pipeline to break up the critical path, reducing the number of multiplexers by re-organizing the hierarchy, or optimizing a certain data path that is identified to be the bottleneck. Doing all this in the nML model, the RTL and the Software Development Kit (SDK) will stay in sync at all times. Synthesis-in-the-loop, enabled by ASIP Designer and its integration with the implementation flow, allows for an iterative and profiling-based approach for PPA optimization and is a key methodology for any processor design project.

PPA optimization using Synthesis-in-the-Loop

Figure 3: PPA optimization using Synthesis-in-the-Loop

Implementation is accompanied by verification. ASIP Designer supports sophisticated verification, offering a combination of formal checks and dynamic tests. The newly released white paper Designing ASIPs with Confidence: A Perspective on the Verification of Application-Specific Instruction Set Processors is a great overview on what it takes to verify an ASIP, and how ASIP Designer supports this process.

For verification, access to Synopsys' leading technology becomes a key asset. ASIP Designer comes with a tight link to VCS simulation, and the Verdi hardware / software debug solution. It is possible to run an application on the RTL implementation (by simulation or emulation) and then co-debug the software and hardware, examine application variables in the Eclipse IDE and at the same time see any hardware signal value in a Verdi waveform viewer. When stepping forward or backward through instructions in the Eclipse IDE the corresponding time is shown in the waveform viewer. Likewise, when selecting the time in the waveform viewer it is also indicated in the software debugger.

The increase in design complexity makes emulation an integral part of the verification flow, augmenting simulator-based verification. Starting with 2020.09, and enhanced with release 2021.03, ASIP Designer supports mapping to a Synopsys ZeBu emulation system, including trace generation for offline  instruction-set simulator (ISS)/ RTL verification, and for Verdi hardware / software co-debugging as described above.

Rapid prototyping is an essential part of almost any chip design. ASIP Designer's integration with virtual prototypes, provides a very flexible and configurable way to integrate the ISS by automatically generating the appropriate SystemC interfaces at the right level of abstraction. Such ISS can be either cycle-accurate or instruction-accurate, both automatically generated from the same single nML model. The simulation models are generated such that they can leverage Synopsys Virtualizer’s unique multicore simulation capability, resulting in fastest overall execution speed. They also support multi-core cross-triggering within Virtualizer, for any combination of ASIPs and other (third-party) cores. 

Support for Virtualizer’s software analysis features

Figure 4: Support for Virtualizer’s software analysis features

For FPGA-based prototyping, ASIP Designer comes with a tight integration with Synopsys HAPS system. This includes the necessary scripts for ProtoCompiler and full support for on-chip debugging. Any embedded software developer developing code for the ASIP core can use the same GUI regardless of the underlying simulation technology which might be the ISS, a HAPS prototyping system, or an RTL simulator.

When talking about the benefit of being part of the world’s largest EDA company, we must not forget internal quality testing, which is part of the ISO9001-certified product development process. For ASIP Designer, we run a huge set of regression tests each night, to make sure any enhancement to the tool does not impact the correctness, or quality of the results. This is enabled by having access to the Synopsys internal pool of synthesis and simulation licenses, and the Synopsys compute farms.  

These few examples illustrate that ASIP Designer is tightly integrated into Synopsys Silicon-to-Software solutions. ASIP Designer’s design methodology is tightly connected to industry-leading implementation and verification tools, and the ASIP Designer R&D and Application Engineering teams are in close contact with the experts that know how to use these technologies, adding real value to the benefit of our customer. 

What’s New: ASIP Designer 2021.03 Release Update

Example Models

Designers can choose from an extensive library of example ASIP models provided as nML source code. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration, and customer-specific production designs.

  • Trv: Four additional RISC-V ISA models, supporting the F single-precision float instruction class, featuring 32-bit data paths, and both a 3- and 5-stage pipeline
  • All Trv models come with optional On-Chip Debugging (OCD) support. The OCD interface uses the automation provided with ASIP Designer, so it is automatically updated for any extensions / modifications made to the Trv models
  • ASIP Designer allows the integration of existing RTL components. A new example model illustrates how to integrate a multi-cycle Verilog component. It shows how to use Verilator to build the ISS, making the integration of an existing RTL component into your ASIP simpler than ever
  • ASIP Designer supports the integration of the ISS into Virtualizer. A new demo setup illustrating the simultaneous debugging and cross-triggering of a multicore system including a standard processor IP (ARC or Arm) and an ASIP is provided

Processor Modeling

  • The nML language has been extended with components, which are parametrized nML blocks that can be instantiated multiple times. nML components allow to efficiently describe parallel instruction slots having a similar structure, as often found in VLIW / ILP architectures
  • For the documentation generation from nML, annotations can now directly be added in an attribute annotated to the nML rules. For example, it is less prone to errors in the documentation when the behavior of a rule is changed, since both behavior and documentation are closely together in the same file

C/C++ Compiler

ASIP Designer comes with a unique and patented compiler solution, with the compiler automatically retargeting itself to the processor architecture. This eliminates any need for compiler backend customization by the user. Release 2021.03 offers

  • Precise I/O constraint modeling for scheduling, both in terms of dependency lengths, affected instructions, and affected variables.
  • Constant pools relative to the global pointer, to load large literals from memory in a position-independent-code (PIC) way
  • The LLVM-based front-end, and all example models featuring the LLVM-based frontend have been updated to the most recent LLVM version 12.0. The newlib component in the full library stack has been upgraded to version 4.0

RTL Generation, Verification, and Synthesis Support

  • PPA estimation for primitive functions, using an easily customizable nML wrapper that generates a minimal processor context as a light but realistic environment for synthesis. This allows to explore design alternatives for such primitive functions using a quickly generated, real synthesis result, avoiding the need to synthesize the entire processor model for trustworthy results on which implementation decisions can be based
  • Simplified integration of a SystemC-wrapped ISS for use in SystemVerilog  test-benches, which  includes the automatic generation of an RCD monitor that compares outputs from RTL and ISS.
  • Alternatively, the RTL can be instrumented to generate traces, even during emulation, that allow to replay its behavior with an ISS, comparing outputs “off-line”
  • Generation of a scripting environment to perform design exploration with Synopsys RTL Architect, enabling an efficient analysis of the generated RTL code

Additional Resources

Customer References