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Synopsys’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.
This bi-annual newsletter provides you with easy access to ASIP-related resources.
Designing an ASIP is all about designing a processor optimized for power, performance and area (PPA) with an instruction-set tailored for a domain or set of applications. An efficient ASIP design methodology, therefore, has to support a tight integration with synthesis and verification flows. As a part of Synopsys’ broad portfolio of solutions, ASIP Designer™ strongly leverages access to Synopsys design and verification methodologies, tools, and expertise.
Examples include hardware implementation analysis and PPA refinement with RTL Architect, the generation of optimized synthesis scripts for Fusion Compiler and Design Compiler® NXT, hardware/software debug support with Verdi®, fast emulation with ZeBu® Server, and a tight link with prototyping solutions, including Virtualizer™ virtual prototyping and HAPS® FPGA-based prototyping.
The generation of fully synthesizable RTL from the nML model is an integral part of ASIP Designer. nML enables both the instruction set as well as the microarchitecture of your design to be defined, which has an obvious impact on the generated RTL. ASIP Designer’s RTL generation can be steered towards certain optimization goals, with many options to choose from. The 2020.03 release introduced a new interactive table that simplifies the selection of these options, providing filtering and search functionalities and direct access to the option’s description.
With the availability of synthesizable RTL, PPA performance is no longer an abstract term, but it is possible to measure, applying the real RTL-to-GDSII tool flow. To accelerate this step, ASIP Designer automatically generates the scripts for Synopsys Design Compiler NXT and Fusion Compiler according to the Synopsys Reference Implementation Flow.
Given ASIP architectures can be fairly large (and ASIP Designer can handle extremely complex designs), full synthesis and routing can take its time. When still in the architecture exploration phase, i.e. exploring the PPA impact of different architectural alternatives, it is often desired to shorten that cycle not using the final results, but very close estimates. That is why with 2021.03, ASIP Designer also integrates with the newly released RTL Architect tool from Synopsys. RTL Architect predicts the power, performance, area and congestion impact of RTL changes. Its estimates get close to the final implementation, as it leverages the algorithms of the Fusion Compiler platform, while taking only a portion of the time of full synthesis and routing. RTL Architect is tailored to analyze and compare alternative implementations, so it becomes an excellent solution during this phase of the design process.
We refer to this methodology as synthesis-in-the-loop™: It is about generating RTL as early as possible in the design process, to make sure that PPA implications and routing congestions are identified early, when they are still cheap to fix. This might identify the need to modify the depth of the pipeline to break up the critical path, reducing the number of multiplexers by re-organizing the hierarchy, or optimizing a certain data path that is identified to be the bottleneck. Doing all this in the nML model, the RTL and the Software Development Kit (SDK) will stay in sync at all times. Synthesis-in-the-loop, enabled by ASIP Designer and its integration with the implementation flow, allows for an iterative and profiling-based approach for PPA optimization and is a key methodology for any processor design project.