ASIP Seminar Europe 2021

ASIP Designer Seminar Europe



Domain-Specific Processor Design using ASIP Designer

The slowing down of Moore’s law and Dennard scaling drives a need for heterogeneous multicore designs, which see a combination of standard processors and processors tuned for a specific workload. These domain-specific processors, also referred to as application-specific processors (ASIPs), implement a specialized instruction set architecture (ISA) tailored to the application, often starting from a baseline ISA such as RISC-V.  

Join us for this free 2h Virtual Seminar to learn more about the power of ASIPs, and how ASIP Designer makes them a reality. The seminar will cover the architectural options to choose from when designing an ASIP. Using examples from the extensive processor model library that comes with ASIP Designer, we will explain the different concepts of parallelization and specialization, and the tradeoffs that come with it. The seminar will include demonstrations of ASIP Designer as well as an investigation of multiple example designs from the DSP, security, and AI domains.

  • An Introduction to ASIP Designer
  • RISC-V ISA example models, and the concept of Simple Datapath eXtensions (SDX)
  • Case study: Designing a programmable AI accelerator for MobileNet V3

If you are a design engineer, algorithm developer, software engineer, system architect, or design manager focusing on advanced SoCs requiring application-specific optimizations, you won’t want to miss this event.




10:00 - 10:20

An Introduction to Domain-Specific Processors, and ASIP Designer

Markus Willems, Sr. Mgr. Product Marketing, Synopsys Germany

Domain-specific processors (also referred to as Application-specific processors, or ASIPs) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs, and will provide an overview of Synopsys' ASIP Designer tool-suite. 

10:20 – 11:20

RISC-V ISA Example Models, and the Concept of Simple Datapath eXtensions (SDX)    

Patrick Verbist, Sr. FAE, Synopsys Belgium

ASIP Designer comes with an extensive library of example ASIP models. These include a wide range of models supporting the RISC-V ISA specification, featuring both 32-bit and 64-bit datapath implementations and various pipeline depths. As the models are provided in nML source code, users are free to modify the processors to customize the ISA and the microarchitecture to their application-specific needs.

For a certain class of instructions, it is now easier than ever to implement such customization of the RISC-V ISA, thanks to ASIP Designer’s SDX approach. Trv-SDX is a new example processor model that implements the RISC-V ISA, and additionally contains user-modifiable-templates for extension instructions.  These templates are encoded using the RISC-V custom-2 opcode space, which has been reserved by the standard to enable custom ISA extensions. The ASIP designer only has to define the behavior of the desired extension instructions in bit-accurate C code.  This makes the concept of ISA extensions simple to define and use

This session will provide an overview of the RISC-V example models, and will demonstrate how the SDX approach allows to quickly design, implement and program, covering three different accelerators featuring FFT, SHA secure hashing and keyword spotting using a neural network.

11:20 - 12:00

Case study: Designing a Programmable AI Accelerator for MobileNet V3 

Dominik Auras, Sr. CAE, Synopsys Germany

To fully maximize the benefits that the ASIP approach makes possible, it is important to be able to consider a wider range of architectural options beyond just simple instruction extension.   For example, both data-level and instruction-level parallelism are important features of advanced ASIPs as well as more highly optimized specialization within datapaths beyond what is possible with simple instruction extension of a fixed base processor.

The power that can be unleashed by ASIP Designer by deploying such architectural design techniques will be illustrated by an example AI processor tuned for the efficient processing of MobileNet graphs. It extends from one of the many RISC-V ISA example models provided in ASIP Designer’s example library, and eventually results in an ASIP with a 4-slot architecture (capable of dispatching 4 instructions in each cycle), that also provides for a 64-MAC vector unit which operates on 8-bit vector data.  Further optimizations are illustrated by showing how the memory access scheme is tuned to the application.
The design process is illustrated starting from an analysis of the algorithm, its suitability for parallelization, and how ASIP Designer’s SDK and RTL generation capabilities allow for an efficient design of a MobileNet ASIP which remains fully C-programmable.