Seminar: Domain-Specific Processor Design using ASIP Designer

Join us December 9, 2019
12:30 - 5:30 pm (lunch included)

800 N. Mary Ave. Bldg. 1
Sunnyvale, CA 94085

Parking is available in the Synopsys parking garage. View the campus map for details. 

The RISC-V initiative has raised increased awareness about the design of domain-specific or application-specific processors, which implement a specialized instruction set architecture (ISA), often starting from a baseline ISA such as RISC-V.

But designers are faced with the challenges of determining the best ISA for their specific application, how to get to a compiler and a simulator for the specialized architecture, and how to know if the target performance can be reached.

Synopsys ASIP Designer is a design tool that automates the design of application-specific processors. Starting from a single processor specification that allows to model standard ISAs such as RISC-V as well as any kind of specializations, designers get a cycle-accurate simulator, debugger and an optimizing C/C++ Compiler, all supporting the specialized ISA. This allows for a compiler-in-the-loop based tuning of the processor specification, using the real application code to benchmark the performance. From the same specification, the RTL code is generated, which allows to measure the gate count and to identify critical paths in the design.

Top semiconductor and systems companies worldwide deploy ASIP Designer for innovative designs on aggressive schedules with limited design teams.

Join us for this free half day seminar, beginning with a networking lunch and followed by technical presentations from Synopsys technical experts on topics including 5G, AI, and security.





12:30 - 1:30


1:30 – 2:15

Getting started … Application-Specific Processors (ASIPs) in System-on-Chip Design: Market and Technology Trends
Markus Willems, Synopsys Germany

ASIPs have established themselves as an implementation option next to standard processors IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability. This talk will provide an introduction into Synopsys' ASIP Designer tool-suite, targeted markets, business models, and how Synopsys collaborates with university partners in this domain.

2:15 - 3:15

Case study 1: Designing an ASIP for SHA256 secure hashing, starting from a RISC-V ISA specification (Including Tool Demonstration)
David Florez, Sr. CAE, Synopsys USA

Many embedded applications rely on hashing algorithms to transmit and to store data in a safe way.  In these contexts, the hashing of data has to be executed at the rate used for the transmission of the data over a channel or when stored to a solid-state memory.  At these high rates, ASIPs are an efficient way to implement hashing algorithms.  We will look at how a standard algorithm, SHA256, can be accelerated by combining custom data paths, register and memory structures with instruction and data level parallelism.

3:15 – 3:30

Coffee Break

3:30 - 4:30

Case study 2: Designing Application-Specific Processors for Deep Learning Acceleration (Including Tool Demonstration)
Gert Goossens, Sr. Director R&D, Synopsys Belgium

Deep learning is making its way into various application domains. The embedded vision market has embraced deep learning algorithms based on convolutional neural networks (CNN). Algorithms capturing dynamic temporal behavior in the form of recurrent neural networks (RNN) are being applied for sound processing and language translation systems. In such a dynamic environment, traditional SoC architectures with a microprocessor and hardwired accelerators no longer suffice. We will illustrate by example how ASIPs reconcile the needs for performance and flexibility. We will present ASIP architectures for two deep learning functions: (i) the acceleration of activation functions in LSTM networks, and (ii) simultaneous localization and mapping (SLAM).

4:30 – 5:15

Case study 3: Minimum Mean Square Error (MMSE) Equalization in 5G New Radio
David Florez, Sr. CAE, Synopsys USA

ASIPs see strong adoption in the field of 5G wireless communication: they enable product development before the 5G standard is finally frozen, and at the same time provide the acceleration needed to achieve the high throughput and short latency requirements of 5G.  We will show the design of an ASIP for MMSE in 5G New Radio.  We follow an “algorithm first” design process that starts from a number of algorithms for which the architecture has to be optimized, and the definition of the throughput requirements.  The presentation will provide an overview on main functional kernels of the MMSE algorithm, and the performance requirement in the context of the 5G standard. We will illustrate the architectural decisions that have to be taken, and how this process is being supported by ASIP Designer. 

5:15 - 5:30