Synplify Premier provides ASIC and SoC designers with several features that help accelerate development of a semiconductor prototype. One of the first challenges faced by designers is the replacement of non-FPGA-based portions of the designs, such as memories, clock configurations and ASIC test circuitry. Synplify Premier provides an easy methodology for handling side files in addition to parsing multiple language formats and constraints files. The next challenge is the importing and handling of 3rd party, Synopsys and internally developed IP, which Synplify Premier automates to significantly increase productivity. Finally, Synplify Premier automates clock conversion so that an ASIC design can fit into the clock structures of an FPGA.
For more Information on ASIC Conversion, download the white paper.