High-Performance, Mid-Range, and Ultra-Low Power RISC-V Processor IP

Synopsys ARC-V Processor IP™ is based on the open standard RISC-V instruction set architecture (ISA), extending the current ARC portfolio and giving customers access to the growing RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.

To accelerate software development, the ARC-V processors are supported by the trusted Synopsys MetaWare Development Toolkit. In addition, Synopsys’ extensive portfolio of EDA tools provide an out-of-the-box development and verification environment to help design and fully verify RISC-V-based SoCs.

Come visit us at Embedded World 2024 in the RISC-V Pavilion, Hall 5, Stand 5-119, to learn more about ARC-V Processor IP.

Key Benefits

scale

Power & Area Efficient

Achieve maximum performance with minimum power and area consumption

configurability

Configurable

Optimize PPA of each processor instance

reliable

Extensible Instruction Set

Make application-specific customizations

speed

Broad Ecosystem

Achieve faster time to market

What's New

ARC-V Processor IP Families

Resources

Quotes from Synopsys ARC Customers and Partners

Talk with an IP Expert