As Moore’s law slows and the semiconductor industry approaches the limits of physics, new techniques and technologies have emerged to enable continued innovation. Nanometers will eventually make way for angstroms to deliver even greater density in much smaller form factors. At these sizes, the need for computational lithography can only grow.
Computational lithography is a resource-intensive undertaking, typically requiring massive data centers to handle the calculations and simulation runs involved. The process could take many, many hours, even when using the most powerful computers. As designers aim to pack more transistors onto their chips, further increasing the challenges of photolithography, computational workloads will only grow. The simulation aspect of computational lithography is one of the most time-consuming parts of this process. Simulation is applied to detailed models of each step in the lithographic process. With potentially millions of small tiles in a full-chip application, it’s imperative to have super-fast computational speed for mask synthesis.
To achieve the needed performance uplift, cuLitho has been integrated into the Synopsys Proteus™ full-chip mask synthesis solution and Synopsys Proteus ILT inverse lithography technology, and optimized to run on the latest generation NVIDIA Hopper™ architecture GPUs. The Proteus mask synthesis solution performs full-chip proximity correction, building models for correction and analyzing proximity effects on both corrected and uncorrected IC layout patterns. The Proteus ILT solution uses inverse imaging technology to resolve challenging optimal proximity effects at advanced technology nodes, helping to identify the optimal mask shapes to print the design intent on the silicon wafer.
Rather than requiring 40,000 CPU systems under traditional configurations, the Proteus solutions running on the cuLitho platform require only 500 NVIDIA DGX™ H100 energy-efficient GPU systems. All parts of the computational lithography process can run in parallel, reducing power requirements and runtimes from weeks down to days. In addition to reduced environmental impact from the data centers, the solution also enables faster simulation runs, which can improve both time to market and quality of results of the silicon.