TLM Library for ARM IP

Enabling Virtual Prototyping for ARM Powered Designs

Synopsys provides product development teams with a comprehensive set of transaction-level models (TLMs) of ARM IP that serve as the building blocks of virtual prototypes. Virtual prototypes are fully functional software models of complete embedded systems, enabling pre-RTL embedded software development and software-driven system validation. The ability to co-design hardware and software through virtual prototypes significantly reduces the product design cycle and speeds time-to-market. Along with the Virtualizer™ tool set's advanced debug and analysis capabilities, designers can take advantage of the performance and early availability of the models to accelerate virtual prototype development, enabling them to start software design up to 12 months before first silicon is available.

ARM Cortex Fast Models

These functionally accurate ARM Instruction Set Models are fully validated by ARM against ARM processor designs and include modeling of advanced ARM technologies such as TrustZone and VFP.

The ARM Cortex Fast Models are available from Synopsys and fully integrated in Synopsys Virtualizer to benefit from the high debug and analysis efficiency through system-level software debug and analysis, hardware/software combined analysis and synchronized integration with 3rd party software debuggers and embedded software development tools.

ARM Classic Processor Models

Synopsys provides a wide variety of TLM-2.0 LT and fast-timed models for ARM Classic processors which include ARM11, ARM9 and ARM7 processor families.

System IP Models

Besides processors, interface IP and peripheral blocks are required to build complex SoCs. Synopsys provides functionally accurate representations of ARM CoreLink interconnect and peripheral IP to speed up virtual prototype assembly so that software developers can focus on the actual benefits of using virtual prototypes rather than building them.

Computer screen showing Transaction-level Model for ARM IP

Transaction-Level Model for ARM IP