Algorithm Design and Analysis

Digital Signal Processing Algorithm Design & Optimization

Algorithm design is an essential element of the digital signal processing (DSP) development process for applications such as wireless telephony, multimedia codecs, DSL and cable modems.

To a large degree, the algorithms you develop have a significant impact on the performance and functionality that differentiates your product.

System Studio, SPW and the companion DSP Model Libraries deliver the highest performance simulation combined with powerful analysis and debug capability for unmatched productivity for signal processing designers.

Benefits

Design Productivity

  • Model-based design: easy-to-use, unified development environment with graphical and language abstractions that capture the entire system in a hierarchical fashion
  • More than 3000 signal-processing models, from simple to very complex
  • Easy integration of existing functions written in C / C++
  • Fixed-point modeling using standard IEEE 1666 SystemC fixed-point data types
  • Native SystemC language support
  • Automatic documentation generation, guarantees consistency between simulation model and paper documentation
  • Complete physical layer simulation chain for the 3GPP LTE standard, including both FDD and TDD modes using the LTE model library
  • Powerful scripting capabilities

Simulation Performance

  • Stream-Driven Simulation™: vector-based processing of static and dynamic dataflow
  • Ultra-fast fixed-point simulation, achieving up to 200x over the OSCI proof-of-concept implementation
  • Fast specification of your algorithm using model-based design, featuring C data flow (CDF) support
  • Compiled simulation
  • Stream-Driven Simulation™: vector-based processing of static and dynamic dataflow
  • Ultra-high capacity, enabling simulations of the most complex signal processing applications

Design Flow Integration

  • SystemC export of algorithm subsystems for integration into any SystemC-based simulation environment
  • Automatic RTL code generation directly from your algorithm description; no need for maintaining parallel libraries
  • Automatic code generation for high-level synthesis, enabling highly-optimized hardware implementations tailored to FPGAs and ASICs.
  • Automated co-simulation setup with RTL simulation tools, allowing easy integration of VHDL/Verilog into the system-level simulation
  • Slave-able simulation interface enables you to plug your algorithm design into the simulation environment of your choice.