Silicon Photonics has the potential to offer a high-performance and low power solution for the electrical interconnect bottleneck. As one of the key optoelectronic building blocks, high speed silicon optical modulators compatible with established CMOS fabrication infrastructure have been extensively studied recently. This example demonstrates the simulation of a 3D Mach-Zehnder Modulator (MZM) implemented on silicon-on-insulator, using Synopsys’ Sentaurus TCAD and RSoft tools.
The MZM involves electronic, process, and optical physics. A complete MZM simulation must incorporate all of these effects.
The MZM has interleaved PN junctions which require full 3D analysis for both the electrical and optical properties.
A mixed-level simulation solution combining Synopsys’ Sentaurus TCAD and RSoft tools offers a complete and rigorous 3D MZM design solution.
Sentaurus TCAD’s SDE or SProcess module is first used to create the geometry. Then, SDE is used to determine the complex index perturbation due to free-carrier absorption at an applied voltage. This creates a TDR file containing the index perturbation.
The MZM structure is automatically and dynamically imported into the RSoft CAD via the TDR file.
RSoft’s BeamPROP is used to compute the modes of the structure, and then simulate the optical phase change through a small section of the modulator arm.
SWB flow. Step 1: structure is drawn and carrier index perturbation is computed in SDE.
Step 2: RSoft optical calculation.
Index Profile of MZM at Y=2.2um (left) and two cuts along Z at X=-2um at different voltages (right).
Mode profile for Ex (left) and Hy (right).
The resulting output phase differences for the bias voltages simulated.
BeamPROP is run at multiple bias voltage points, from -3 to 0V, to produce a plot of the output phase vs. bias voltage for the MZM.
This data can be used to calculate the analytic modulator response, or other useful quantities such as the phase shift efficiency Vπ ∗ Lπ.
 D. Marris-Morini, et al., "Low loss 40 Gbit/s silicon modulator based on interleaved junctions and fabricated on 300 mm SOI wafers", Optics Express 21 No. 19 (2013), 22471-22475