Library characterization plays a key role in the drive towards achieving higher power, performance, and area (PPA) metrics in less design time. A large portion of chip area consists of digital logic, memories, I/O, and custom IP designed and implemented by static timing analysis-based digital methodologies that use Liberty models that are derived from library characterization. Therefore, the ability to characterize libraries efficiently and accurately across all intended PVT conditions is a critical requirement for full-chip or block-level design flows.
Cell library characterization produces the following outputs:
Verilog models are most often used in the design and verification of digital circuits at the register-transfer level of abstraction. These Verilog models are further synthesized into the gate-level netlist.
IBIS is the standard for describing the analog behavior of buffers of the digital IC’s pins (input, output, and I/O buffers) in plain ASCII-formatted text (behavioral model) without revealing the underlying circuit’s structure or process information. Advantages of IBIS include:
- Faster SI simulation (reflections, jitter, eye diagram analysis) compared to SPICE (~10x faster)
- Allows PI simulation using IBIS 5.0 (simultaneous switching output [SSO] noise simulation)
- Protect intellectual property (IP), impossible to “reverse engineer” the circuit from IBIS model
- Portable data model, a standard interface and syntax for convenient description
The Liberty format is an ASCII file that describes a cell’s characterized data in a standard way. This file is used both by the synthesis tools and by the place-and-route tools. It simply describes the overall structure of the file. Liberty file format is very complex with huge numbers of special statements that can describe all sorts of parameters that would be relevant to the different CAD tools that use this format to get information about the standard cells in the library.
The Liberty model consists of delay, transition time, tristate, input capacitance, hidden power, dynamic power, leakage power, setup time, hold time, recovery time, removal, minimum pulse width, output current waveform, input receiver capacitance, power supply waveforms, ground waveforms, leakage current, gate leakage current, CCB output voltage waveform, CCB input miller capacitance, CCB noise propagation model, statistical models, and moment models.