Electromigration is the movement of atoms based on the flow of current through a material. If the current density is high enough, the heat dissipated within the material will repeatedly break atoms from the structure and move them. This will create both ‘vacancies’ and ‘deposits’. The vacancies can grow and eventually break circuit connections resulting in open-circuits, while the deposits can grow and eventually close circuit connections resulting in short-circuit.

Electromigration current density

How does electromigration work?

Uniform electromigration within metallization lines, if it could be maintained, would not be damaging. In steady-state, no damage should be observed other than at the beginning and end of the metallization line. This is because along the metallization line the number of atoms arriving in a given local volume is equal to the number of atoms leaving the volume.

Metallization line

Damage to the metallization lines is caused by divergences in atomic flux. When the amounts of matter leaving and entering a given volume are unequal, the associated accumulation or loss of material results in damage. This results in two types of inequalities:

  1. Depletion of atoms (Voids): Slow reduction of connectivity; Interconnect failure
  2. Deposition of atoms (Hillocks): Shorts
Failures caused by electromigration

The existing solution to avoid electromigration is to ensure that wires with potential large current densities have proper widths to hold them. Due to chemical-mechanical polishing (CMP) effects which reduces the thickness of wires, a thinner wire may be able to hold a larger current density than a wider one. So there could be more than one ranges of EM compliant widths for a wire that has a large current density. Current density tables are typically used to calculate EM compliant widths.

In a design, net routing always needs to meet various constraints, such as EM and resistance constraints. An automatic methodology of checking EM and resistance constraints is needed to improve their designer productivity. With such capability, users then can check their routing results at any stage of the routing flow and make adjustments accordingly to achieve EM and resistance constraints compliance. 

The EM constraint tells us how much current a connection object can sustain continuously to achieve a predefined mean time to failure (MTTF). There are 4 types of EM constraints for the 4 kinds of equivalent currents below:

  1. The absolute current
  2. The average current
  3. The peak current
  4. The root-mean-square (RMS) current 

To do an EM constraint check for a net, designers define the equivalent current of this type for each analog or digital cell pin, according to which the EM/R checking engine calculates the equivalent current of this type for each connection object of the net and then performs the following checks: 

  • Use a current density table for the corresponding EM type supplied by the user to determine the proper width ranges to carry the current for each connection object of a net. If the actual width isn’t within any EM compliant width range, a flag is sent to the user or routing results should be automatically adjusted. 
  • Use via current tolerance constraints for the corresponding EM type supplied by the user to determine the min number of cut to carry the current for each via of a net. If the actual value is smaller than the EM compliant min number of cuts, a flag is sent to the user or routing results should be automatically adjusted.

Factors affecting electromigration:

  • Wire Material. It is known that pure copper used for Cu-metallization is more electromigration-robust than aluminum. Copper wires can withstand approximately five times more current density than aluminum wires while assuming similar reliability requirements
  • Wire Temperature. In Black’s equation, which is used to compute the mean time to failure of metal lines, the temperature of the conductor appears in the exponent, i.e. it strongly affects the MTTF of the interconnect. The temperature of the interconnect is mainly a result of the chip environment temperature, self-heating effect of the current flow, heat of the neighboring interconnects or transistors, and thermal conductivity of the surrounding materials.


Black’s Equation: MTTF= CJ-ne(Ea/kT) where

•      C= a constant based on metal line properties;

•      J = the current density;

•      n = integer constant from 1 to 2

•      T = temperature in deg K;

•      k = the Boltzmann constant; and

•      Ea = Activation Energy 


  • Wire Size. As Black’s equation shows, apart from the temperature, it is the current density that constitutes the main parameter affecting the MTTF of a wire. Since the current density is obtained as the ratio of current I and cross-sectional area A, and since most process technologies assume a constant thickness of the printed interconnects, it is the wire width that exerts a direct influence on current density: The wider the wire, the smaller the current density and the greater the resistance to electromigration.

If the frequency is less than a critical value f0 = ½(MTFdc), the interconnect will follow a DC electromigration behavior. System fails even before the onset of reverse current. A gradual improvement in MTF happens as frequency is increased above f0. This is due to increased effectiveness of damage healing during reverse period.

At the beginning of positive and negative pulses, atoms and vacancies start to migrate along grain boundaries and interfaces. This migration can recover with opposing stress. A shorter stress period means a relatively small displacement of atoms and vacancies, which is easy to be healed.

Within a very high frequency range, the damage healing process can overcome all defects which are brought during the other half period. However, an interconnect is never immortal. It can fail because of temperature gradients only. In this case Joule Heating sets the lifetime based on RMS current density. Waveform of a stress also has an impact on failure rates. For example, local melting will happen and cause failures for very large peak current densities even if the RMS current density is not very high.

Electromigration and Synopsys

Synopsys offers electromigration analysis solutions for both digital and custom design environments:

  • IC Compiler™ II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next-generation designs across all market verticals and process technologies while enabling unprecedented productivity. IC Compiler II includes innovations for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, dynamic, power shaping, signal electromigration, manufacturing compliance, and signoff closure. 
  • Fusion Compiler™ is the next generation RTL-to-GDSII implementation system architected to address the complexities of advanced process node design and deliver up to 20% improved quality-of-results (QoR) while reducing time-to-results (TTR) by 2X. Fusion Compiler’s integrated cockpit provides a comprehensive platform for design including RTL physical synthesis, design planning, placement, clock tree synthesis (CTS), advanced routing, signal electromigration, physical synthesis-based optimization, chip finishing, signoff quality analysis and ECO optimization.
  • The IC Compiler™ II / Fusion Compiler with RedHawk™ Analysis Fusion integration introduces in-design power integrity analysis (including power rail electromigration) and fixing capabilities in designers' flows offering signoff accuracy results during the physical design step. 
  • PrimeSim XA for transistor level electromigration and power integrity analysis. PrimeSim EMIR provides a complete set of analysis tools for device-level and interconnect reliability analysis; including IR drop, current density and electromigration, and device aging.

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