Monday, May 8, 2023
5:30 p.m. - 7:30 p.m.
Wednesday, May 10, 2023
4:15 p.m. - 5:35 p.m.
Structural Test Over HSIO on the ATS 7038 Massively Parallel SLT Platform
Jess Gillespie and Redentor Nova, Advantest
This demonstration will detail how to achieve cost-effective structural test (SCAN, MBIST, LBIST, etc.) over a functional high-speed IO (HSIO) interface, using key building blocks of Advantest System Level Test technology, which can be leveraged to test more than 700 DFT-enabled DUTs simultaneously on Advantest’s ATS 7038 SLT platform. It also demonstrates the seamless portability to the SLT platform of the structural test patterns developed for the V93000 ATE platform. Executing scan test over standard HSIO protocols such as USB, the SoC/DUT requires special design-for-test IP embedded during the design phase. As Advantest has partnered with Synopsys for this effort, the demo uses Synopsys’ SLM High-Speed Access and Test (HSAT) IP and TestMAX ALE software with Xilinx’s ZCU102 FPGA to emulate the DUT; driven by Advantest’s Single Board Computer (SBC) and ActivATE™ test management software.
New Cutting-Edge Adaptive Test Analytics Applications Based on an Innovative, First-of-Its-Kind, Closed-Loop Real-Time ACS Edge Analytics and Control Process
Both applications highlighted in this paper focus on improving quality by reducing DPPM but in uniquely different ways that are highly differentiated from other quality-centric analytics, such as DPAT. This paper will cover two applications. The first is an adaptive test flow wafer stacked map generated during wafer sort tests, which can reveal a potential reliability issue in a specific zonal region of the wafer. The map enables deployment to production by executing extra tests during final test on risky parts coming from this zonal area to ensure quality without escalating test time. The second application is an adaptive test limit, which looks at the correlation in the analytics environment between a VDD consumption test and Sensor LPLVT-N result on each die and generates a formula on the edge with a guard band for low and high limits based on this bi-variate correlation plot.
HVM test of UCIe-enabled chiplets for 2.5D and 3D devices: The case for a dedicated test port
This paper will give a brief overview of the new UCIe standard for chiplets and related DFT and BIST features. It will also elaborate on a proposal for a dedicated test port for ATE connection to chiplets. References to recently developed scan bus architectures will be made as well as a connection to the IEEE 1838 standard for 3D IC test which proposes a flexible parallel port (FPP) as path for high-bandwidth test access in volume production.