Why Attend?

The Advantest VOICE Developer Conference unites semiconductor test professionals representing the world's leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements, express new ideas, share best practices and network with one another.

Who Attends?

Semiconductor test professionals representing the world's leading companies in:

Integrated Device Manufacturers (IDMs)


Fabless Semiconductor Companies

Outsourced Semiconductor Assembly and Test (OSAT) Providers

Synopsys at VOICE 2023

Technology Kiosk Showcase
Monday, May 8, 2023
5:30 p.m. - 7:30 p.m.
Wednesday, May 10, 2023
4:15 p.m. - 5:35 p.m.
Structural Test Over HSIO on the ATS 7038 Massively Parallel SLT Platform

Jess Gillespie and Redentor Nova, Advantest

This demonstration will detail how to achieve cost-effective structural test (SCAN, MBIST, LBIST, etc.) over a functional high-speed IO (HSIO) interface, using key building blocks of Advantest System Level Test technology, which can be leveraged to test more than 700 DFT-enabled DUTs simultaneously on Advantest’s ATS 7038 SLT platform. It also demonstrates the seamless portability to the SLT platform of the structural test patterns developed for the V93000 ATE platform. Executing scan test over standard HSIO protocols such as USB, the SoC/DUT requires special design-for-test IP embedded during the design phase. As Advantest has partnered with Synopsys for this effort, the demo uses Synopsys’ SLM High-Speed Access and Test (HSAT) IP and TestMAX ALE software with Xilinx’s ZCU102 FPGA to emulate the DUT; driven by Advantest’s Single Board Computer (SBC)  and ActivATE™ test management software.


Technical Paper

New Cutting-Edge Adaptive Test Analytics Applications Based on an Innovative, First-of-Its-Kind, Closed-Loop Real-Time ACS Edge Analytics and Control Process​

Both applications highlighted in this paper focus on improving quality by reducing DPPM but in uniquely different ways that are highly differentiated from other quality-centric analytics, such as DPAT. This paper will cover two applications. The first is an adaptive test flow wafer stacked map generated during wafer sort tests, which can reveal a potential reliability issue in a specific zonal region of the wafer. The map enables deployment to production by executing extra tests during final test on risky parts coming from this zonal area to ensure quality without escalating test time. The second application is an adaptive test limit, which looks at the correlation in the analytics environment between a VDD consumption test and Sensor LPLVT-N result on each die and generates a formula on the edge with a guard band for low and high limits based on this bi-variate correlation plot. ​​


Technical Paper

HVM test of UCIe-enabled chiplets for 2.5D and 3D devices: The case for a dedicated test port

This paper will give a brief overview of the new UCIe standard for chiplets and related DFT and BIST features. It will also elaborate on a proposal for a dedicated test port for ATE connection to chiplets. References to recently developed scan bus architectures will be made as well as a connection to the IEEE 1838 standard for 3D IC test which proposes a flexible parallel port (FPP) as path for high-bandwidth test access in volume production. 

Booth Presentations & Demonstrations:

SLM High-Speed Access & Test (HSAT)

SLM High-Speed Access & Test (HSAT) has an adaptive learning engine for efficient and high quality testing. It provides high bandwidth testing over functional interfaces with high-speed access to DFT and a silicon monitoring network throughout the entire silicon lifecycle.

Adaptive Test Analytics
Synopsys has partnered with Advantest to provide a new adaptive test analytics applications based on a complete closed-loop real-time ACS Edge analytics and control process flow. The demonstration will show how  to improve quality by reducing DPPM that’s uniquely different from DPAT. The first adaptive test application presents higher chip quality with negligible throughput impact. The second adaptive test application incorporates additional sensor data for to help make more informed decisions for improving quality.