Why Attend?

The Advantest VOICE Developer Conference unites semiconductor test professionals representing the world's leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements, express new ideas, share best practices and network with one another.

Who Attends?

Semiconductor test professionals representing the world's leading companies in:


Integrated Device Manufacturers (IDMs)


Fabless Semiconductor Companies

Outsourced Semiconductor Assembly and Test (OSAT) Providers

Synopsys at VOICE 2024

Technology Kiosk Showcase
Monday, June 3, 2024
5:30 p.m. - 7:30 p.m.
Wednesday, June 5, 2024
4:15 p.m. - 5:35 p.m.
Synopsys Path Margin Monitor for Silicon Lifecycle Management

Mohsin Ali, Advantest & Synopsys

Over the life of a device, degradation of critical-path timing margins can be caused by such factors as frequent toggling and voltage-, current- and temperature-related stress. In addition to “one-time” characterization of margins on ATE to judge the design quality, monitoring margins during a chip lifecycle can help us detect critical conditions, prevent field failure of devices, and improve future devices by, for instance, adjusting the manufacturing process or design. This kiosk introduces Path Margin Monitor (PMM) developed by Synopsys as part of its integrated Silicon Lifecycle Management (SLM) platform. It features the test program/library developed by Advantest that utilizes PMM to characterize devices, as well as a hardware demo showcasing the current functionality and the data available to users from PMM modules. This information can then be used during testing and lifecycle of the device for lifecycle/performance management.

Booth Presentations & Demonstrations:

Synopsys SLM HSAT with Synopsys TestMAX ALE and TestMAX DFT

This demonstration will highlight the seamless integration of Synopsys products SLM HSAT IP, TestMAX ALE, and TestMAX DFT including specific capabilities of Streaming Fabric (SF) and Sequential Compression (SEQ) to provide a scalable end-to-end test solution. Synopsys SLM HSAT IP enables high-speed access to DFT networks over existing functional high-speed interfaces allowing for scan test over all phases of the silicon lifecycle. The Synopsys TestMAX ALE software works with our SLM HSAT IP for ATPG pattern translation and reverse mapping of the scan chain output.  The SF feature is a bandwidth optimized test bus that connects to each design core to deliver packetized SCAN data. The SEQ feature is a PRPG-based sequential SCAN compression that is scalable to designs of any size and can be re-configured as LBIST for in-system-test applications. This combined solution provides improved test bandwidth and throughput with a reduced test pin count, enhanced test coverage and access to the test network throughout the silicon lifecycle.  

Synopsys and Advantest Adaptive Test Analytics
This demonstration will highlight two adaptive test analytics applications based on a complete closed loop real-time data collection and control process leveraging the Advantest Cloud Solutions™ (ACS) Real-Time Data Infrastructure (RTDI) platform and Synopsys Silicon.da solution. The demonstration will show how to improve test efficiency / coverage and chip quality. The first adaptive test application is Data Feed Forward that leverages previous stage results to predict and optimize ongoing stage test efficiency or coverage. The second adaptive test application is Final Test – Part Average Test (FT-PAT) which reduces Defective Part Per Million (DPPM) at FT enabling real-time re-binning based on a Dynamic PAT (DPAT) algorithm for improved chip quality.