Join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing's mask synthesis, mask data prep, and lithography simulation solutions.

Why Attend?

Synopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis, Mask Data Preparation, TCAD, and Yield Management tools provide leading edge performance, accuracy, quality, and cost of ownership for all your production and development needs.

Who Should Attend?

The Synopsys Technical Forum provides OPC, RET, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware.


12:30 - 1:00 PM
Registration & Lunch

Shankar Krishnamoorthy

GM, Corp Staff


Welcome & Introduction

Monday, February 26, 2024
1:00 p.m. - 1:15 p.m. PT

Distinguished Speaker - The Future of Semiconductor Manufacturing: New Developments in Speed and Innovation

Monday, February 26, 2024
1:15 p.m. - 1:45 p.m. PT

As the miniaturization of advanced logic processes continues, the time from design to commercialization is lengthening.​ This is due to the increasing difficulty of the manufacturing process, design, and verification associated with the growing complexity of device structures. However, LSIs, such as processors and accelerators for AI, are evolving at a rapid pace and must be commercialized in a short period of time to meet time-to-market requirements. We will introduce the Rapidus model, which solves this problem and achieves short TAT manufacturing.

Dr. Kazunari Ishimaru

Senior Managing Executive Officer

Silicon Technology Division, Rapidus Corp.

Jerry Chen

Deputy Director

E-Beam Operations Division, TSMC

Keynote - Data Preparation Evolution and Mask Quality Enhancement

Monday, February 26, 2024
1:45 p.m. - 2:15 p.m. PT

As technology evolves, we are facing many new challenges, such as data structure, tight pitches, complex model OPC and ILT, which cause file expansion and longer data handling cycle time. The topic of discussion will cover the evolution of our data preparation center and what we are doing to prepare for the full chip ILT and curvilinear era.   With the abundance of data information we have, we can apply it to mask writing, inspection, and repairing, and further improve the quality of mask making in a more efficient and reliable way.

Progress on Curvilinear OPC at Intel

Monday, February 26, 2024
2:15 p.m. - 2:45 p.m. PT

Curvilinear masks have long been discussed in the literature as a disruptive transition that will improve patterning in many ways. After over a decade of promise, the transition to curvilinear masks is here. In this talk, we will share the latest data from Intel. We will review the benefits of curvilinear and how that differs between 193nm and EUV layers. We will also discuss the current challenges, and strategies used to overcome those challenges.

Dr. Harsha Grunes

Senior Principal Engineer


MS Chiang

Principal Engineer


Advanced Correction Technologies to Optimize Memory Cell Performance

Monday, February 26, 2024
2:45 p.m. - 3:15 p.m. PT

With the evolution of semiconductor technology, an increasing number of RET tools have been developed to improve the imaging and quality of patterns. Winbond has closely collaborated with Synopsys in recent years, achieving notable results. First, a Hybrid ILT Solution was developed with Synopsys, combining Manhattan and curve linear patterns to achieve an optimal balance between mask write time and quality. Second, with Synopsys' TOPILT solution, optimal-sized dummy patterns were successfully added around critical patterns, significantly enhancing the process window. Third, due to the precise predictability of Slitho, a collaboration with Synopsys integrated the Slitho model with SNPS's ILT/OPC tools. This integration successfully predicted the CD size of unfriendly patterns, substantially improving the CD range.

Advances in Computational Lithography Solutions for High NA EUV Manufacturing

Monday, February 26, 2024
3:15 p.m. - 3:45 p.m. PT

The path to a viable EUV manufacturing solution has been long and difficult, requiring substantial innovation by the lithography community over multiple decades.  The fruits of that labor are upon the industry, with EUV becoming a critical, enabling step in modern semiconductor manufacturing processes. A new set of challenges present themselves to the industry as we look to achieve even higher resolution with ‘high-NA’ EUV tools. Fortunately, computational lithography solutions for high-NA tools exist, and can accelerate learning and understanding prior to widespread access to physical machines. This paper will discuss the modifications to computational lithography modeling and its flows, needed to enable manufacturing with high-NA EUV tools.

Dr. Michael Lam

Director R&D


3:45 - 4:45 PM
Thank You & Prize Drawing - Dessert Reception


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Synopsys Booth #717

Visit our Synopsys Booth to view the latest innovative technologies and chat with Synopsys experts live during the exhibition on February 27-28!

Please visit our conference presentations and course page to learn more about Synopsys at SPIE Advanced Lithography + Patterning 2024,

Synopsys Presentations