All members of the design and test community are invited to attend Synopsys 28th Annual Test & SLM Special Interest Group (SIG) at the 2022 International Test Conference (ITC). This year’s event will be hosted by Dr. Ken Butler, Senior Director of Business Development from Advantest.  Dr. Butler will be joined by experts from leading companies who will describe how Synopsys’ comprehensive Test and SLM solutions are enabling them to achieve their quality and reliability goals.

Attendees will also have the opportunity to meet with Synopsys experts to discuss and learn more about Test and SLM technologies. Appetizers and cocktails will be served, followed by a sit-down dinner and prize drawings!

 

Seating is limited, so please register early for this exciting and informative event (ITC registration is not required).

Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event

 

Monday, September 26, 2022
6:30 p.m. - 10:00 p.m.

The Westin Anaheim Resort
1030 West Katella Avenue, Anaheim, CA 92802

 

Synopsys at ITC


Exhibit Hours

Tuesday, September 27
10:30am - 5:30pm

Wednesday, September 28
9:30am - 4:30pm

Thursday, September 29
9:30am - 1:00pm

Visit the Synopsys Booth

The Synopsys TestMAX™ family offers innovative test and diagnosis for all silicon designs and enables a unified flow within the Synopsys’ Digital Design Family. Synopsys TestMAX works in conjunction with the latest Synopsys Silicon Lifecyle Management (SLM) technology for enhanced in-chip observability, silicon health and analytics, meeting both design and test goals concurrently.

This year we will be highlighting groundbreaking Test and SLM technologies that encompass integrated tools, IP and methodologies which enable optimized quality, performance and reliability at each phase of the device lifecycle from in-design, in-ramp, in-production and in-field.

Synopsys Participation in Technical Programs


Thursday, 9/29

IEEE International Workshop on Silicon Lifecycle Management

Friday, 9/30

IEEE Automotive Reliability and Test & Safety Workshop

Poster Sessions

Wednesday, September 28th 12:30 -2:00 p.m.


Accelerating Design Cycle with DFT and Test Coverage Analysis at RTL
  • Michael Arneson, Micron
  • Rahul Singhal, Synopsys
  • Sruthi Nanduru, Synopsys
Re-targeting Block-Level Patterns Using Top-Level On-Chip Clock Controller (OCC) --- An Industrial Case Study
  • Zhanwei Zhong, Sounil Biswas, Amit Wangoo, Manish Bhattarai, Marvell
  • Anand Gangwar, Synopsys
Advanced Core Wrapping for Power, Early Test Coverage and Automation
  • Anand Gangwar, Fenil Shukla, Krishnakanth Bachu, Synopsys
Speedup Logic Diagnosis with Static Layout Data
  • Ruifeng Guo, Synopsys
A Novel DFT [Design for Test] Clock Gating Technique to Reduce Power Consumption
  • Shwetha Murthy, Paul Policke, Qualcomm
  • Anand Gangwar, Fenil Shukla, Synopsys
Design-for-Diagnosis for Multiple Defects per Chain
  • Emil Gizdarski, Yasunari Kanzawa, Synopsys
Leveraging Existing High Speed Functional Serial Interfaces for Testing & Monitoring Silicon Throughout the Entire Lifecycle
  • Klaus Hilliges, Advantest
  • Amit Pandey, Brendan Tully, Amazon
  • Ash Patel, Ramsay Allen, Synopsys

For more information about Synopsys’ comprehensive test solution, visit synopsys.com/test