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All members of the design and test community are invited to attend Synopsys 28th Annual Test & SLM Special Interest Group (SIG) at the 2022 International Test Conference (ITC). This year’s event will be hosted by Dr. Ken Butler, Senior Director of Business Development from Advantest. Dr. Butler will be joined by experts from leading companies who will describe how Synopsys’ comprehensive Test and SLM solutions are enabling them to achieve their quality and reliability goals.
Attendees will also have the opportunity to meet with Synopsys experts to discuss and learn more about Test and SLM technologies. Appetizers and cocktails will be served, followed by a sit-down dinner and prize drawings!
Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
Monday, September 26, 2022
6:30 p.m. - 10:00 p.m.
The Westin Anaheim Resort
1030 West Katella Avenue, Anaheim, CA 92802
Online registration has closed, however, walk-ins will be accommodated on-site as space permits
Agenda
6:30 p.m. - 7:15 p.m.
7:15 p.m. - 7:30 p.m.
7:30 p.m. - 9:00 p.m.
9:00 p.m. - 9:05 p.m.
9:05 p.m. - 10:00 p.m.
Cocktail Reception & hors d'oeuvres
Welcome by Dr. Ken Butler, Advantest
Presentations by: Samsung, Enfabrica, Advantest and Synopsys
Raffle drawing
Dessert & Coffee
Synopsys at International Test Conference (ITC)
Exhibit Hours
Tuesday, September 27
10:30 a.m. - 5:30 p.m.
Wednesday, September 28
9:30 a.m. - 4:30 p.m.
Thursday, September 29
9:30 a.m. - 1:00 p.m.
Visit the Synopsys Booth
The Synopsys TestMAX™ family offers innovative test and diagnosis for all silicon designs and enables a unified flow within the Synopsys’ Digital Design Family. Synopsys TestMAX works in conjunction with the latest Synopsys Silicon Lifecyle Management (SLM) technology for enhanced in-chip observability, silicon health and analytics, meeting both design and test goals concurrently.
This year we will be highlighting groundbreaking Test and SLM technologies that encompass integrated tools, IP and methodologies which enable optimized quality, performance and reliability at each phase of the device lifecycle from in-design, in-ramp, in-production and in-field.
See demonstrations on:
- Advanced Logic/Memory Test
- Functional Fault Simulation
- Scan Test Over PCIe/USB/SPI
- SLM Analytics at the Edge
If you are interested in scheduling an on-site meeting with Synopsys representatives, please contact us:
Vendor Session
Tuesday, September 27
12:00pm - 12:30pm
Corporate Forum Track
Test and Analytics: Enabling Silicon Lifecycle Management
Synopsys Participation in Technical Programs
Thursday, September 29
Friday, September 30
IEEE International Workshop on Silicon Lifecycle Management
IEEE Automotive Reliability and Test & Safety Workshop
Technical Sessions
2:00 p.m. - 3:30 p.m.
Session E1:
Special Session Dedicated to the Memory of Tom W. Williams, Wojciech Maly and Dhiraj Pradhan
4:00 p.m. - 5:30 p.m.
Session C2:
New Frontiers in Test Content Optimization
C2.1 Automatic Structural Test Generation for Analog Circuits using Neural Twins
4:00 p.m. - 5:30 p.m.
Session E2:
Special Session: Experiences in Silicon Lifecycle Management
E2.2 Sensor Aware Production Testing
11:00 a.m. - 2:30 p.m.
Session E3:
Industrial Practices I
E3.1 Application of Sampling in Industrial Analog Defect Simulation
4:30 p.m. - 6:00 p.m.
Session C5 Panel 3:
Performing RAS in Today’s Mission Critical Systems
10:30 a.m. - 12:00 p.m.
Special Session C6:
Road to Chiplets: UCIe
1:30 p.m. - 3:00 p.m.
Session D7 Panel 4:
Automotive Safety & Security Interoperability
B7.3 Comprehensive Power-Aware ATPG Methodology for Complex Low-power Designs
E7.3 Selective Multiple Capture Test (SMART) XLBIST
SLM Workshop (Silicon Lifecycle Management)
General Chair: Yervant Zorian, Synopsys
5:15 p.m. - 6:15 p.m.
Paper:
High Speed IO Access for Test Forms the Foundation for Silicon Lifecycle Management
8:30 a.m. - 10:10 a.m.
Paper:
An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories
8:30 a.m. - 10:10 a.m.
Paper:
Silicon Lifecycle Management Optimizes Vmin Search Enabling Efficient & Reliable Chip Operation
ARTS Workshop (Automotive Reliability Test & Safety)
General Chair: Yervant Zorian, Synopsys
5:10 p.m. - 6:30 p.m.
Technical Session 1:
Functional Safety Solutions
Empowering Secure and Reliable BIST Solution for Automotive SoC
8:30 a.m. - 9:20 a.m.
Keynote 2:
Evolution and Trends Driving the Automotive Architecture and Ecosystems of the Future
1:00 p.m. - 2:15 p.m.
Special Session:
The Accellera Functional Safety Standard: Enabling Automation, Interoperability and Traceability
9:20 a.m. - 10:10 a.m.
Paper 1:
A Novel Protection Technique for Embedded Memories with Optimized PPA
Poster Sessions
Wednesday, September 28
12:30 p.m. - 2:00 p.m.
Accelerating Design Cycle with DFT and Test Coverage Analysis at RTL
- Michael Arneson, Micron
- Rahul Singhal, Synopsys
- Sruthi Nanduru, Synopsys
Re-targeting Block-Level Patterns Using Top-Level On-Chip Clock Controller (OCC) --- An Industrial Case Study
- Zhanwei Zhong, Sounil Biswas, Amit Wangoo, Manish Bhattarai, Marvell
- Anand Gangwar, Synopsys
Advanced Core Wrapping for Power, Early Test Coverage and Automation
- Anand Gangwar, Fenil Shukla, Krishnakanth Bachu, Synopsys
A Novel DFT [Design for Test] Clock Gating Technique to Reduce Power Consumption
- Shwetha Murthy, Paul Policke, Qualcomm
- Anand Gangwar, Fenil Shukla, Synopsys
Design-for-Diagnosis for Multiple Defects per Chain
- Emil Gizdarski, Yasunari Kanzawa, Synopsys
Leveraging Existing High Speed Functional Serial Interfaces for Testing & Monitoring Silicon Throughout the Entire Lifecycle
- Klaus Hilliges, Advantest
- Amit Pandey, Brendan Tully, Amazon
- Ash Patel, Ramsay Allen, Synopsys
For more information about Synopsys’ comprehensive test solution, visit synopsys.com/test
