AMS SIG India 2023 Proceedings

A 3nm Custom SRAM Layout Efficiency Improvement using User Defined Devices (UDD)

Ramesh Halli, Jigar Patel - MediaTek

As technology shrinks custom layout development is getting complex and time consuming. Layout Designer develop layout using the foundry provided PCell, which doesn’t meet all foundry guideline. Hence the designers spend a lot of time for creating layout with the default PCells. With innovative way of User Defined Device (UDD) facilitate in Layout productivity enhancement by creating user required PCells in a graphical manner.

Synopsys Full Custom Flow for Analog SoC Design

Tushar Bhattacharya - AB Circuits and Research Labs

ABCRL is an Automotive Electronics start-up doing our first chip design for a non-functional-safety application.The application has Analog Front End sensing requirements and simple digital processing and data forwarding to a network processor. The SoC is being developed using Global Foundries 130BCD technology and will go into an MCM package with dies procured from third-party vendors. For this project, we used Synopsys Custom flow for the very first time. All analog simulations were done using PrimeSim HSPICE in the PrimeWave environment and Schematics and Layouts were developed in Custom Compiler. In this talk, we will share our experience as first-time users of Custom Compiler.

Effective Mixed Signal Verification Methodology for SerDes IP

Chirag Aggarwal - STMicroelectronics​

SerDes IPs are quintessential for Mobile, IoT, High Performance Computing and many other high-speed applications. From verification perspective, because of the large size of the IP and sizable digital controller and the need to verify the IP in entirely, it’s important to have a robust mixed signal environment for complete validation of the IP. In this presentation, we will discuss about the challenges of SerDes verification and our verification methodology.