ISO 26262 ASIL B & D Ready Certified IP for Automotive ADAS

The growing demand for safety-critical Advanced Driver Assistance Systems (ADAS) for pedestrian detection/avoidance, lane departure warning/correction, traffic sign recognition, surround view, drowsiness monitoring and other applications, is requiring a new class of SoCs. Incorporating the latest interface standards, running multiple vision base algorithms and combining diverse sensor inputs add additional challenges for designers to support real-time multimedia, vision co-processing, and sensor fusion subsystems.

Synopsys’ portfolio of Automotive Safety Integrity Level (ASIL) B and D Ready ISO 26262 certified DesignWare IP with safety packages helps designers overcome the challenges of implementing the application-specific IP requirements, accelerate their ISO 26262 SoC-level functional safety assessments and reach target ASILs. In addition to complying to the ISO 26262 Functional Safety standards, Synopsys provides IP that meets the advanced features, small area, high performance and low power requirements of ADAS applications.

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DesignWare IP for ADAS SoCs Block Diagram

Highlights

Low latency, multi-port LPDDR5/4 controller and PHY supporting speeds up to 6400 Mbps offers multi-port access to shared main memory, enabling protocol engines for embedded vision and high-performance heterogeneous processing.
Configurable Ethernet QoS controller is optimized for low latency and supports high-performance automotive applications requiring audio video bridging including the new Time Sensitive Networking (TSN) standards.
MIPI D-PHY and MIPI CSI-2 and DSI controllers meet the latest MIPI specifications and enable multiple camera and display scenarios while meeting power and area requirements.
PCI Express® controllers and PHY is optimized for power, performance and area with data protection and reliability features.
CCIX IP solution, including controller, PHY, and verification IP, supports data transfer speeds up to 25 Gbps (ready for 32 Gbps) and cache coherency for faster data access
Security IP for cryptography and protocol acceleration including platform security and secure boot.
UFS host controller IP provides high-throughput, low-power, low-latency embedded and removable storage.
HDMI PHY and controller IP, compliant with the latest HDMI 2.1 specification, delivers the highest digital video & audio experience.
HPC Design Kit with embedded memories optimized for SoC processors: CPU, GPU and DSP are designed for demanding electro migration conditions.
STAR Memory System offers ECC support for multi-bit error correction.
Sensor & Control IP Subsystem optimized to process data from digital and analog sensors and offload host processors to enable more power-efficient processing of the sensor data is implemented using Synopsys’ 32-bit ARC® EM processor.
EV Vision Processor offers multicore architecture for object detection implementing convolutional neural network (CNN) with OpenCV and OpenVX software programming environments.
ARC EM, HS, and EV Functional Safety Processor IP supports ISO 26262 functional safety applications with integrated hardware safety features.
12-bit SAR ADC offers high resolution up to 12-bit, 320MSPS ADC/DAC converters with high dynamic range and high speed for extended application range.