IP for Automotive ADAS

ISO 26262 ASIL B & D Ready Certified IP for Automotive ADAS

The growing demand for safety-critical Advanced Driver Assistance Systems (ADAS) for pedestrian detection/avoidance, lane departure warning/correction, traffic sign recognition, surround view, drowsiness monitoring and other applications, is requiring a new class of SoCs. Incorporating the latest interface standards, running multiple vision base algorithms and combining diverse sensor inputs add additional challenges for designers to support real-time multimedia, vision co-processing, and sensor fusion subsystems.

Synopsys’ portfolio of Automotive Safety Integrity Level (ASIL) B and D Ready ISO 26262 certified DesignWare IP with safety packages helps designers overcome the challenges of implementing the application-specific IP requirements, accelerate their ISO 26262 SoC-level functional safety assessments and reach target ASILs. In addition to complying to the ISO 26262 Functional Safety standards, Synopsys provides IP that meets the advanced features, small area, high performance and low power requirements of ADAS applications.

Mouse over or tap to learn more about DesignWare IP solutions: 

MIPI D-PHY

HDMI

  • HDMI 1.4 and 2.0 compliant controller and PHY IP
  • Configurable modes support dual-mode or Tx/Rx-only
  • Supports Mobile High-Definition Link (MHL) interface
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PCIe PHY & Controller

  • PCIe root port / endpoint with RAS features
  • High-performance, multi-standard PCIe PHY
  • Configurable PCIe Controller for PCIe 3.1, 2.1 & 1.1
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LPDDR4/DDR4 PHY & Controller

Ethernet

  • 10/100/1000 Ethernet controller supporting Audio Video Bridging
  • Ideal for real-time, multimedia automotive networks
  • Support for IEEE 1588-2002/2008 for networked clk synch
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SATA PHY & Controller

EV Vision Processor

  • Fully programmable & configurable vision processor
  • Object detection engine for convolutional neural network
  • Supports OpenCV libraries providing >2500 functions
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Sensor & Control IP Subsystem

  • Optimized to process data from digital and analog sensors
  • Offload host processors for power efficient processing
  • ARC EM ISO 26262 Functional Safety Package
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AMBA Interconnect

  • Interconnect IP for ARM® AMBA® 4 AXI, ACE-lite™, AXI3™, AHB™, APB™
  • Automated AMBA subsystem assembly
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Embedded Memories and Logic Libraries

Advanced Peripherals GPIO, SPI/QSPI

  • Popular industry-standard interfaces
  • Highly configurable to meet specific design requirements
  • DMA hardware handshaking I/F compatible w/ ARM® AMBA® peripheral
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Advanced Peripherals UART

  • Popular industry standard interface
  • Highly configurable to meet specific design requirements
  • DMA hardware handshaking I/F compatible w/ ARM® AMBA® peripheral
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SD/eMMC

  • Storage Host Controller optimized for low power, high performance storage
  • Fully configurable multi-protocol support
  • Supports optional integrated DMA
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Datapath

  • Achieve area and power reduction using optimized datapath logic
  • Over 40 instantiable blocks for multimedia and image processing
  • Data-tracking pipeline management technology to reduce power consumption
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ADCs & DACs

  • High-performance, high-speed 10- and 12-bit at 320 MSPS ADCs
  • General-purpose, high-resolution ADCs, auxiliary DACs and VDACs
  • Ideal analog interface for automotive microcontrollers
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Security

CPU

  • 32-bit multicore ARC processors for ADAS & infotainment
  • Add custom instructions for automotive protocols
  • Available in dual- and quad-core with I and D caches or cacheless configurations
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Highlights

  • Low latency, multi-port LPDDR4 controller and PHY supporting speeds up to 3200 Mbps offers multi-port access to shared main memory, enabling protocol engines for embedded vision and high-performance heterogeneous processing.
  • Configurable Ethernet QoS controller is optimized for low latency and supports high-performance automotive applications requiring audio video bridging including the new Time Sensitive Networking (TSN) standards.
  • MIPI D-PHY and MIPI CSI-2 and DSI controllers meet the latest MIPI specifications and enable multiple camera and display scenarios while meeting power and area requirements.
  • Security IP for cryptography and protocol acceleration including platform security and secure boot.
  • HPC Design Kit with embedded memories optimized for SoC processors: CPU, GPU and DSP are designed for demanding electro migration conditions.
  • STAR Memory System offers ECC support for multi-bit error correction.
  • Sensor & Control IP Subsystem optimized to process data from digital and analog sensors and offload host processors to enable more power-efficient processing of the sensor data is implemented using Synopsys’ 32-bit ARC® EM processor.
  • EV Vision Processor offers multicore architecture for object detection implementing convolutional neural network (CNN) with OpenCV and OpenVX software programming environments.
  • 32-bit ARC EM Processor with Safety Enhancement Package (SEP) and ARC EM Safety Island IP supports ISO 26262 Functional Safety applications with integrated hardware safety features.
  • PCI Express® controllers and PHY is optimized for power, performance and area with data protection and reliability features.
  • SATA 6G Host and Device controller and PHY support both SATA and eSATA including AHCI programming model support multiple ports.
  • 12-bit SAR ADC offers high resolution up to 12-bit, 320MSPS ADC/DAC converters with high dynamic range and high speed for extended application range.