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The DesignWare® Ethernet Quality-of-Service (QoS) Controller IP implements the link layer of an OSI Ethernet system. The silicon-proven core is configurable and scalable to meet multiple Ethernet application requirements. Synopsys offers a high-quality IP solution that is in volume production and has been successfully implemented in a wide range of applications.
The DesignWare Ethernet QoS Controller IP is designed to support high-performance applications requiring audio video (AV) bridging, data center bridging, and advanced segmentation offloading features such as automotive IVI chips, set-top box chips, and network routers. This offloading is accomplished by removing any latency associated with configurable IP.
Typical design of configurable IP results in multiple layers that are bridged during configuration. Using multiple layers results in many unnecessary latencies due to double buffering of data as it crosses from one layer to another. The coreConsultant configuration tool removes the latencies at configuration time, thus providing high-performance IP.  DesignWare Ethernet Quality-of-Service Datasheet
- Compliant with IEEE 802.3 specifications
- Support for IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
- Supports IEEE 802.1-AS-2011, and IEEE 802.1-Qav-2009, version for AV traffic
- Supports separate channels or queues for AV data transfer in 100 Mbps and 1000 Mbps modes
- Supports configuring up to eight additional channels on transmit and receive paths for AV traffic
- Supports IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for additional transmit channels
- Provides separate DMA, TxFIFO, and RxFIFO (MTL) for each additional channel while maintain the system side interface (AHB, AXI, or native)
- Supports IEEE 802.3-az-2012 for Energy Efficient Ethernet (EEE)
- Supports data center bridging features, including:
- Separate channels or queues for DCB data transfer in 100 Mbps and 1000 Mbps modes
- Up to eight queues on the Transmit and Receive paths for DCB traffic
- The following Tx queues scheduling mechanisms meet the compliancy specification in IEEE 802.1- Qaz Enhanced Transmission Selection (ETS) algorithm:
- Weighted Round Robin (WRR)
- Deficit Weighted Round Robin (DWRR)
- Weighted Fair Queuing (WFQ)
- Strict Priority (SP)
- Common memory for all selected Tx or Rx queues
- Programmable control to route received VLAN tagged non-AV packets to channels or queues
- Selectable number of Tx DMA channels with TCP Segmentation Offload (TSO) enabled
- Supports AMBA 2.0 for AHB Master/Slave ports
- Supports AMBA 3.0 for AXI Master/Slave ports
- Supports APB3 Slave interface for CSR access
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