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DesignWare Ethernet Quality-of-Service Controller IP
The DesignWare® Ethernet Quality-of-Service (QoS) Controller IP supports 1M, 10M and 1G speeds and implements the link layer of an Open Systems Interconnection (OSI) Ethernet system. The silicon-proven configurable and scalable IP is shipping in volume and has been successfully implemented in a wide range of Ethernet applications.
The DesignWare Ethernet QoS Controller IP is designed to support high-performance applications requiring audio video bridging including the new Time Sensitive Networking (TSN) standards, data center bridging, and advanced segmentation offloading features such as automotive In-Vehicle Infotainment (IVI)/Advanced Driver Assistance Systems (ADAS) chips, set-top box chips, and network routers. This offloading is accomplished by removing any latency associated with configurable IP.
Typical design of configurable IP results in multiple layers that are bridged during configuration. Using multiple layers results in many unnecessary latencies due to double buffering of data as it crosses from one layer to another. The coreConsultant configuration tool removes the latencies at configuration time, thus providing high-performance IP.
The DesignWare Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.
DesignWare Ethernet Quality-of-Service Datasheet
| Fast Ethernet QoS IP Prototyping & Integration with DesignWare IP Prototyping Kits Reduce Ethernet QoS IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box. |
Highlights
Products
Downloads and Documentation
- Compliant with IEEE 802.3 specifications
- Support for IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
- Supports IEEE 802.1-AS-2011, and IEEE 802.1-Qav-2009, version for AV traffic
- Supports separate channels or queues for AV data transfer in 100 Mbps and 1000 Mbps modes
- Supports configuring up to eight additional channels on transmit and receive paths for AV traffic
- Supports IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for additional transmit channels
- Provides separate DMA, TxFIFO, and RxFIFO (MTL) for each additional channel while maintain the system side interface (AHB, AXI, or native)
- Supports IEEE 802.3-az-2012 for Energy Efficient Ethernet (EEE)
- Supports data center bridging features, including:
- Separate channels or queues for DCB data transfer in 100 Mbps and 1000 Mbps modes
- Up to eight queues on the Transmit and Receive paths for DCB traffic
- The following Tx queues scheduling mechanisms meet the compliancy specification in IEEE 802.1- Qaz Enhanced Transmission Selection (ETS) algorithm:
- Weighted Round Robin (WRR)
- Deficit Weighted Round Robin (DWRR)
- Weighted Fair Queuing (WFQ)
- Strict Priority (SP)
- Common memory for all selected Tx or Rx queues
- Programmable control to route received VLAN tagged non-AV packets to channels or queues
- Selectable number of Tx DMA channels with TCP Segmentation Offload (TSO) enabled
- Supports AMBA 2.0 for AHB Master/Slave ports
- Supports AMBA 3.0 for AXI Master/Slave ports
- Supports APB3 Slave interface for CSR access