Events

Dec

Synopsys Aerospace and Defense Verification Seminar

The overall complexity and size of FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life.

Security checking, DO-254 design assurance, superior performance of Verilog and VHDL, UVM methodologies, MATLAB integration, static and formal verification solutions, verification intent specification and traceability, advanced debug capabilities, total coverage models, fault injection capabilities and Triple Modular Redundancy (TMR) for error detection and mitigation for FPGA design flows are methods that have become a requirement in today’s FPGA Aerospace and Defense products.

  • Nov 20, 2018 
  • Herzliya, Israel

Functional Safety Test for Automotive SoCs Workshop

Join us to gain insights on new and emerging functional safety test methods for the most efficient automotive system-on-chips (SoCs) and ICs.

  • Nov 27, 2018 
  • Munich, Germany

SemIsrael

SemIsrael Expo 2018 is the #1 Professional Semiconductor Event in Israel.
The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 1,000 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design houses, labs and universities.

  • Nov 27, 2018 
  • Airport City, Israel

Synopsys TCAD Reception at IEDM 2018

After a day of IEDM conference sessions, attend the Synopsys reception. It’s a great opportunity for you to relax and enjoy complimentary food and beverages while catching up with colleagues. Don’t miss this chance to ask a Synopsys TCAD staff member your pressing questions.

  • December 4, 2018 
  • San Francisco, CA

ISO 26262 To Semiconductors Conference

Attend this event to hear best practice examples from semiconductor companies on how to best apply functional safety management on chip level. Attend Synopsys’ technical session on Flow for Measuring Diagnostic Coverage in IP Blocks to Reach Target ASILs on December 5, 2018 at 11:40am.

  • December 4-7, 2018 
  • Munich, Germany

IP-SoC 2018

The IP-SoC 2018 conference, fully dedicated to IP and IP-based electronic systems, offers IP providers and IP consumers an opportunity to share information about technology trends, innovative IP SoC products, market changes, and more. Synopsys will present solutions for artificial intelligence, automotive, and security in two presentations: The Marriage of AI and Safety in Automotive SoCs and Security from Silicon to Software.

  • December 5 - 6, 2018 
  • Grenoble, France

Ethernet PHY Design Flow and Custom Compiler Workshop

Hear from the Synopsys DesignWare IP team about the high-speed 56G Ethernet PHY IP design project’s key findings. Get hands-on experience using Custom Compiler’s productive layout features, which helped the team optimize its methodology for successful design and delivery of the 56G Ethernet PHY.

  • December 7, 2018 
  • Mountain View, CA