Verification Futures Conference

The presentation will cover dynamic and formal approaches to verifying RISC-V cores, with topics including, but not limited to: ISA compliance verification and functional coverage, data path validation, functional verification of critical blocks, and security verification.

In this session we will discuss the vision and roadmap of applying AI/ML to chip design and verification from what exists today to the “science fiction” future of Generative AI agents working together and orchestrated to design, verify and debug designs under the guidance of human engineers to further drive innovation beyond what we can imagine today.

This paper presents a systematic methodology for selecting optimal abstraction levels in SystemVerilog modeling, demonstrated through practical case studies. The first example transitions from a SPICE-level operational amplifier to a structural SystemVerilog model using voltage-current-resistance (VIR) nettypes. We demonstrate how controlled sources and basic passive components can preserve essential analog characteristics while achieving a significant TAT speedup.