This paper presents a left-shift performance verification methodology for an automotive multi-die SoC that identifies system-level bottlenecks before RTL is mature, enabling faster architectural iteration and earlier topology decisions. The approach uses a CLI-based automation framework in Platform Architect to manage model setup, workload execution, and KPI analysis, including latency, bandwidth, throughput, and utilization.

To improve accuracy beyond abstract transaction-level models, we integrated a Verilated memory subsystem and custom glue logic to better capture interactions across compute clusters, CMN, memory, and NoCs in both single-die and die-to-die configurations. Across representative workloads, the platform exposed critical issues such as NoC congestion, bandwidth limits, and die-to-die sensitivity to traffic patterns that would likely have appeared much later in RTL validation. This enabled earlier design-space exploration, more informed performance sign-off, and reduced downstream risk.

Texas Instruments and Synopsys jointly developed the Virtualizer Development Kit (VDK) for the TDA5 automotive SoC family, enabling SW developers to build and validate complex multi-domain software stacks for ADAS, Gateway, and Infotainment well before silicon is available. The VDK has already been used to bring up drivers, operating systems, and partner SW stacks and is running in TI’s CI/CD pipelines. By shifting SW development left by 18+ months, the TDA5 VDK accelerates bring-up, supports digital-twin and software-in-the-loop testing, and enables earlier safety validation, setting a new benchmark for pre-silicon enablement.

This presentation explores the architecture and performance of a cache‑coherent, RISC‑V–based High‑Performance Computing (HPC) SoC using Platform Architect. It enabled an early, quantitative trade‑off analysis to balance cache coherence, NoC bandwidth, and HBM4 resources to sustain scalable multi‑core performance without over‑provisioning interconnect or memory resources—or shifting bottlenecks between the NoC, LLC, and HBM subsystems as core counts scale.

The platform model comprises 32 instances of custom RISC‑V processor models executing Linux benchmarks that exert sustained pressure on the shared cache hierarchy, cache‑coherent interconnect, and HBM4 memory subsystem. The platform model was built utilizing the extensive Platform Architect library, including TLM models for caches, NoCs, memory controllers, and integrated Gem5 processor models, enabling rapid architectural exploration prior to RTL availability. Multi‑dimensional analysis—including cache hit/miss behavior, transaction throughput, and NoC and memory utilization—provides insight into scalability limits, coherence‑induced traffic effects, and resource balance across the system. These results demonstrate how executable system‑level models can guide architectural decisions, tune IP parameters, and de‑risk integration choices early in the design flow.

Future work will replace the generic NoC with a vendor‑supplied, higher‑fidelity TLM model to further improve correlation and architectural confidence.

In this talk we illustrate the approach with an automotive‑SOC project and show how VDK enables a single, common virtual environment for early software development across four critical domains—ADAS, IVI, FuSA, and Security.

• Virtual Machine FFI (Freedom From Interference) – guarantees strong isolation among VMs, allowing each functional block (e.g., Android, Linux, Auto/OS) to run independently while sharing the same simulated silicon.
• Boot Sequence Monitoring – provides instant visibility of power‑on, boot‑sequence and initialization metrics, letting teams validate that boot targets are met four‑to‑six months earlier than with physical silicon.
• System Performance Evaluation – captures detailed CPU, major‑IP, bus‑fabric and memory‑subsystem workloads; the data feed a CI/CD loop that refines performance and power models before tape‑out.

These capabilities make MediaTek VDK a pivotal acceleration engine for automotive validation, expanding verification coverage, reducing HW ↔ SW iteration cycles, and shortening time‑to‑market for next‑generation ADAS and autonomous‑driving features. In conclusion, VDK reshapes cross‑team collaboration, turning what used to be a sequential HW‑first flow into a truly concurrent, software‑centric development paradigm.

Optimizing SoC performance requires close coordination across multiple architectural dimensions, including interconnect topology, main memory behavior, throughput and frequency alignment, and representative use‑case analysis.

Locking performance targets early in the design cycle depends on understanding how these elements interact under realistic workloads, rather than evaluating them in isolation.

In this presentation, we show how system‑level performance exploration enables informed trade‑offs and early visibility into bottlenecks, helping teams align architectural decisions with target use cases before downstream implementation constraints set in.

 We discuss several exploration models built and analyzed using Platform Architect (PA), incorporating coherent and non‑coherent interconnects, DDR memory models, custom FT models, and custom STL files to drive realistic traffic.

While the primary focus is early full‑system use‑case de‑risking, a key advantage of the step‑by‑step platform‑building workflow is that useful “pipe‑clean” stages emerge naturally as part of the exploration process.

Using this approach, we uncovered a skid‑buffer sizing bottleneck in a coherent interconnect that was introducing bubbles at main memory, identified NoC reorder‑buffer performance limitations that were not evident from configuration alone, and, in one project, verified an entire SoC fabric topology at the PA level. These activities frontloaded performance feedback that would otherwise surface in later design and verification phases, while also freeing up RTL verification resources to focus on deeper, more targeted testing. The net result is reduced program risk and rework, and faster convergence toward a well‑optimized system solution.

For Texas Instruments' SoC platforms, predicting performance early in the design phase is key for architecture decisions and early customer engagement, especially for performance critical AI benchmark applications. Traditional approaches for pre-silicon performance evaluation suffer either from limited accuracy of spread-sheet based analytical modeling, or from lack of system-level visibility of IP-level RTL simulation, or from late availability of finalized RTL for emulation. This presentation explores the use of Synopsys Platform Architect as a cross-functional solution to provide reliable and detailed performance insights for hardware and software optimization on TI's next-generation TDA5 SoC family.

We showcase a cycle-accurate model of the TDA5 AI Accelerator sub-system in the context of the shared NoC and memory architecture. We build an architecture performance model for HW/SW co-optimization by integrating TI's SystemC model of the C7™ NPU with SystemC TLM models from the Platform Architect model library. This enables the simulation of CNN workloads via the TI Deep Learning (TIDL) toolchain with both high-level performance results and granular visibility into interconnect-level metrics. This work lays the groundwork for a scalable virtual platform approach to SoC performance analysis that can evolve alongside future architecture generations. 

Li Auto shares its practical experience of using VDK in software-defined vehicle development. By building an integrated software–hardware, cross-platform development system, Li Auto enables efficient software migration and collaborative validation across virtual platforms, FPGA prototypes (such as HAPS-200), and real SoCs. The adoption of VDK significantly shifts software development earlier in the lifecycle, improves interface verification and system integration efficiency, reduces silicon respin risks, and accelerates time to market—demonstrating strong compatibility and engineering advantages in complex heterogeneous architectures.