AMBA®CHI New Features for Cache Coherent Verification

VIP Expert

May 30, 2021 / 1 min read

Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.

AMBA®CHI-E built on top of existing AMBA® CHI-D (Issue D) specification (refer to our blog on AMBA®CHI-D), introduces the support for– a set of new transactions, exclusive access features, transaction optimizations, series of performance throughput improvement features and key Arm architecture features.

Some of the new features include:

New Transactions and Exclusives

  • New request transaction types are introduced, such as: ReadPreferUnique, MakeReadUnique, writes with optional data, write zero with no data, two-part stash. Also, new snoop transaction types SnpPreferUnique, Snoop Query are introduced.
  • New coherent exclusive access features are added to improve execution efficiency of exclusive sequences. These are based on request transactions MakeReadUnique, ReadPreferUnique; snoop transactions SnpPreferUnique and Snoop Query.

Transaction Optimization Features

  • New transaction flow optimizations are introduced, such as: direct write-data transfer flow, combined write and CMO transactions, request ordering flow optimizations, treating forwarding snoops as hints at request node, and SLC replacement hint propagation from request node to caches in interconnect.

Performance Throughput Improvement Features

  • Key performance throughput improvement features are introduced, such as: Multiple interfaces for a given component, replicated channels on a single interface, extended transaction ID width to 12 bits, and extension of group ID field.

Arm Architecture Features

  • Memory tagging extensions are introduced to align with Arm v8.5 architecture requirements, a mechanism that can be used to detect memory safety violations.
  • Additional DVM operations are introduced to align with Arm v8.4 architecture.

It’s nice that your system works well when unstressed, but what happens when you’re running at speed and there’s a lot of traffic churning through those coherent networks? Here Synopsys provides a capability called VC VIP Auto Performance which will generate traffic following the AMBA® Adaptive Traffic Profile (AMBA® ATP). (You need to create a test profile as input to this tool.) Subsequently you can analyze for latency and bandwidth problems in Verdi Performance Analyzer.

All the latest features are fully supported and available in Synopsys verification IP for AMBA® 5 CHI. Synopsys solution for AMBA® 5 CHI, provides performance metrics for latency and throughput analysis, comprehensive system level checks for protocol, data integrity and cache coherency. Built-in sequence collection, functional coverage model, verification plans, and a set of usage examples are also included to speed up verification coverage closure. Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer.

More information on Synopsys AMBA® VIP and Test Suites is available at

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