Accelerating ASIP Design & Verification with STMicroelectronics

Patrick Verbist

Jun 14, 2022 / 4 min read

For applications that need highly specialized processing, application-specific instruction-set processors (ASIPs) provide a good solution. From custom processors to programmable hardware accelerators, ASIPs are more computationally efficient than general-purpose processors and offer more flexibility versus fixed-function RTL designs. In other words, the main draw of an ASIP is its specialized architecture, which is designed to efficiently meet the performance specifications for a particular application, such as wireless baseband processing, image signal processing, audio processing, or artificial intelligence (AI).

When offloading an SoC’s microprocessor core, ASIPs deliver benefits in these key areas:

  • Performance increase via architectural specialization and parallelism at the instruction, data, and task levels
  • Power consumption reduction through the above features as well as power-optimized RTL generation and power gating of cores
  • Post-silicon programmability, supporting changing requirements without SoC re-spins and providing fast algorithm mapping from C to silicon with easy debugging

Designing and verifying these devices, however, is not a trivial task, involving many steps. To start off, engineering teams have to define the optimal processor architecture for the application. They also must develop the hardware implementation as well as the associated software development kit (SDK). All this effort highlights the need for a way to accelerate architectural exploration given the time-to-market pressures that designers constantly face.

In this blog post, learn how the Synopsys ASIP Designer tool helped STMicroelectronics to achieve 5x faster design and verification turnaround time while also adhering to safety and security standards for its ASIP design using the new functional safety (FuSa) features in the ASIP Designer tool automation.

IoT Tablet Device

Safeguarding ASIP Designs Against Attacks and Random Faults

Headquartered in Geneva, Switzerland, ST develops chips for an array of industries, from automotive to industrial, as well as selected consumer electronics applications and the IoT. To support increasing demands for SoCs that meet FuSa and security standards, ST develops custom processors. These processors implement mechanisms that satisfy functional safety requirements and protect program execution against physical attacks.

One of the safety mechanisms that ST uses in its processors is the dual-core lockstep (DCLS) architecture implementation. DCLS ASIPs provide logic duplication to help reduce the risks that stem from random faults and to protect against physical attacks. They’re ideal for integration into SoCs for high-reliability applications such as automotive, industrial, aerospace, and healthcare.

To design a DCLS ASIP, engineers must create a second instantiation of the processor core. The control signals in the processor control unit and data path from both instantiations should be in lock step. If they’re not, this could indicate a fault in one of the processors. For example, should a high-energy particle from space or a high-speed electron impact the chip, this could switch or flip a memory cell, causing one of the processors to behave differently.

Acceleration Through Automation

To automate the design and verification process, ST, a long-time user of the ASIP Designer tool suite for developing specialized processors for applications in digital signal processing, control, and security, has extended the use of the tool for its DCLS ASIPs.

“Synopsys ASIP Designer enables us to rapidly explore different instantiations of our dual core, which saves substantial time and effort while ensuring that we have a reliable design for safety-critical applications. The automated tool maximizes productivity of our engineering team, enabling us to meet our customers’ time-to-market demands.” – Anne Merlande, Processor Architecture Expert, ST

Using ASIP Designer, the ST team reduced its design and verification turnaround time by 5x compared to a traditional RTL design flow. Traditionally, designing DCLS processors is a time-consuming endeavor, relying on the manual addition and verification of DCLS features in the processor’s RTL model. With ASIP Designer, the team can model a single ASIP architecture at a higher level, from which the tool automatically generates an RTL model with the full DCLS functionality, including the duplicated ASIP cores and the addition of monitoring logic.

The ST team worked closely with Synopsys to enhance ASIP Designer with new, highly configurable DCLS FuSa and security features. Thanks to the ST team’s domain expertise, the tool’s RTL generation function can be configured easily, without compromising power, performance, or area (PPA). For example, users can specify:

  • The relative delay between the ASIP core instances
  • Additional pipelining of the ASIP core datapath, taking into account the added comparator logic
  • The optional use of duplicate and alternative monitor implementations
  • The desired RTL modularity

“ST has long experienced the engineering productivity benefits of ASIP Designer and its automatic generation of the C compiler, instruction set simulator, debugger, and RTL. As we see a growing demand for high-reliability processors, we closely collaborated with Synopsys, contributing our dedicated domain expertise. With the new DCLS features in Synopsys ASIP Designer, we can rapidly explore different RTL instantiations of our dual-core processors, saving substantial time and effort while ensuring that we have a reliable design for safety-critical applications.” – Christophe Monat, Manager of Computing and Compilers Center, ST

On top of the above DCLS features, ASIP Designer comes with an additional option to automatically insert error detection code (EDC) logic near the registers of the processor, which provides alerts to random faults to further increase device reliability. The RTL implementations generated by ASIP Designer can be readily synthesized with Synopsys Fusion Compiler and other leading design tools. For automotive designs, it’s useful to highlight that Fusion Compiler is a part of the Synopsys automotive Safety-Aware Solution. The tool uses the safety specification format (SSF) to automate FuSa aspects of the SoC design cycle. The SSF describes a common safety intent such as hardware safety mechanisms (e.g., DCLS, EDC, and more), helping to ensure that safety requirements are met and easily traceable at every point in the design process.

Bringing ASIP Design Within Easier Reach

For our Smart Everything world, where more of our devices boast intelligence and connectivity, ASIPs provide a flexible, power-efficient option for specialized processing. And as ST has demonstrated, a tool suite that automates many of the steps for designing and verifying ASIPs solves the time-to-market challenges associated with hand-coding the RTL. The collaboration between ST and Synopsys to enhance ASIP Designer paves the way for more design teams to take advantage of the performance, power, and programmability benefits of ASIPs for specialized applications.

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