To automate the design and verification process, ST, a long-time user of the ASIP Designer tool suite for developing specialized processors for applications in digital signal processing, control, and security, has extended the use of the tool for its DCLS ASIPs.
“Synopsys ASIP Designer enables us to rapidly explore different instantiations of our dual core, which saves substantial time and effort while ensuring that we have a reliable design for safety-critical applications. The automated tool maximizes productivity of our engineering team, enabling us to meet our customers’ time-to-market demands.” – Anne Merlande, Processor Architecture Expert, ST
Using ASIP Designer, the ST team reduced its design and verification turnaround time by 5x compared to a traditional RTL design flow. Traditionally, designing DCLS processors is a time-consuming endeavor, relying on the manual addition and verification of DCLS features in the processor’s RTL model. With ASIP Designer, the team can model a single ASIP architecture at a higher level, from which the tool automatically generates an RTL model with the full DCLS functionality, including the duplicated ASIP cores and the addition of monitoring logic.
The ST team worked closely with Synopsys to enhance ASIP Designer with new, highly configurable DCLS FuSa and security features. Thanks to the ST team’s domain expertise, the tool’s RTL generation function can be configured easily, without compromising power, performance, or area (PPA). For example, users can specify:
- The relative delay between the ASIP core instances
- Additional pipelining of the ASIP core datapath, taking into account the added comparator logic
- The optional use of duplicate and alternative monitor implementations
- The desired RTL modularity
“ST has long experienced the engineering productivity benefits of ASIP Designer and its automatic generation of the C compiler, instruction set simulator, debugger, and RTL. As we see a growing demand for high-reliability processors, we closely collaborated with Synopsys, contributing our dedicated domain expertise. With the new DCLS features in Synopsys ASIP Designer, we can rapidly explore different RTL instantiations of our dual-core processors, saving substantial time and effort while ensuring that we have a reliable design for safety-critical applications.” – Christophe Monat, Manager of Computing and Compilers Center, ST
On top of the above DCLS features, ASIP Designer comes with an additional option to automatically insert error detection code (EDC) logic near the registers of the processor, which provides alerts to random faults to further increase device reliability. The RTL implementations generated by ASIP Designer can be readily synthesized with Synopsys Fusion Compiler and other leading design tools. For automotive designs, it’s useful to highlight that Fusion Compiler is a part of the Synopsys automotive Safety-Aware Solution. The tool uses the safety specification format (SSF) to automate FuSa aspects of the SoC design cycle. The SSF describes a common safety intent such as hardware safety mechanisms (e.g., DCLS, EDC, and more), helping to ensure that safety requirements are met and easily traceable at every point in the design process.